SystemVerilog priority modifier usage

Question

I'm reading about SV priority keyword. I found following example in on of the papers written by Sutherland:

I'm not quite sure why we can see simulation synthesis mismatch if {priority} is NOT used. Lets assume we don't use {priority} and {IRQ} is always one hot. In that case even if DC optimize away the priority encoder logic, sim and synthesis should always match. Isn't it the case? At any time IRQ can take any one of the 4 values.

I'm not sure what I'm missing.

Answer 1

I think there is a mistake in the example -- the case items should be 4'b???1, 4'b??1?, 4'b?1??, and 4'b1???. Then the issue comes down to your assumption about IRQ being one-hot encoded or not. The priority keyword tells the synthesis tool not to assume one-hot.