Questions tagged [vlsi]

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.

In addition, VLSI Technology, Inc was a company which designed and manufactured custom and semi-custom ICs. The company was based in Silicon Valley, with headquarters at 1109 McKay Drive in San Jose, California. Along with LSI Logic, VLSI Technology defined the leading edge of the application-specific integrated circuit (ASIC) business, which accelerated the push of powerful embedded systems into affordable products.

129 questions

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1 answer

ERROR: 'Checker 'xor_module_b' not found. Instantiation 'x0_1' must be of a visible checker.'?

What is this error 'Checker 'xor_module_b' not found. Instantiation 'x0_1' must be of a visible checker.'? I am writing verilog code in behavioral model by using module instantiation. While compiling i am getting the error. Portion of code and…

asked Mar 17 '18 at 16:50

Ankit Mahajan

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1 answer

Input decimal values like 0.0047 in verilog

I have an array of decimal values like 0.0047, -45.34 etc. Is there a way I can add this in verilog and automatically view it's 16 bit converted value?

verilog vlsi system-verilog-assertions

asked Mar 04 '18 at 07:23

Srinath Radhakrishnan

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1 answer

Systolic Array Simulation in Python

I am trying to simulate a systolic array structure -- all of which I learned from these slides: http://web.cecs.pdx.edu/~mperkows/temp/May22/0020.Matrix-multiplication-systolic.pdf -- for matrix multiplication in a Python environment. An integral…

python multithreading signal-processing simulation vlsi

asked Feb 02 '18 at 04:42

sgk525

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1 answer

How to store program permanently in a FPGA?

I was working on a project using FPGA and Arduino, in which i have to show for how long my fpga device was OFF if it was so. I am using BASYS3 FPGA board. Once i switch off my FPGA the program is getting erased.

vhdl verilog fpga vlsi

asked Feb 01 '18 at 10:53

asha.anil

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1 answer

Spice Simulation from Electric on OSX

I'm using Electric as design system. I want to simulate in LTSPICE the designed circuit. I've linked LT Spice and Electric (cmosedu) as the tutorial show (http://cmosedu.com/videos/electric/tutorial1/electric_tutorial_1.htm), but when I try to…

vlsi pspice

asked Dec 09 '17 at 21:14

Pietro La Spada

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1 answer

VHDL Counter returning 'X', unknown value

I am trying to create a 4 bit counter with instantiated components, shown below. When I simulate, the output toggles between 0 and X(an unknown signal). I'm not sure what is wrong. simulations, circuit diagram and code are shown below. 4 Bit modulo…

binary vhdl counter vlsi digital-design

asked Nov 08 '17 at 15:29

Chris

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2 answers

Prepone Region in SystemVerilog

In SystemVerilog simulation, the prepone region is one of the several regions in a given time slot. What is the actual purpose of this region? Can anyone explain this with a valid example?

system-verilog vlsi asic

asked Sep 21 '17 at 02:50

Aravind

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3 answers

Default statement in SystemVerilog Case

I'm trying to understand following scenario: typedef enum logic [2:0] { ONE, TWO, THREE, FOUR, FIVE } enum_t; A case statement with enum_t type in case expression: enum_t case_expression; logic [2:0] result; case (case_expression) ONE:…

verilog system-verilog register-transfer-level vlsi

asked Apr 28 '17 at 20:51

newbie

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couldn't load file "/usr/lib/x86_64-linux-gnu/magic/tcl/tclmagic.so"

I have a problem with running magic vlsi. The problem is couldn't load file "/usr/lib/x86_64-linux-gnu/magic/tcl/tclmagic.so": /usr/lib/x86_64-linux-gnu/magic/tcl/tclmagic.so: undefined symbol: Tk_GetCursorFromData I think this caused by: …

tcl tk-toolkit vlsi

asked Jun 10 '16 at 21:18

Ebraheem Kashkoush

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0 answers

theoretical calculations of delay of a logic gate of 45 nm technology

i had designed a 32 bit mac unit using VHDL in xilinx . now, i want to calculate the delay theoretically and compare with timing report obtained from xilinx is there any specific procedure for calculating delay of the logic gate???

vhdl xilinx vlsi

asked Feb 17 '16 at 06:57

Eswar Chandra

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2 answers

$display vs $strobe vs $monitor in verilog?

What is the difference between $display vs $strobe vs $monitor in verilog? When in the event queue does each apply, and how do the statements interact? Can any statement inhibit another?

verilog vlsi register-transfer-level

asked Sep 28 '15 at 21:27

blitz

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1 answer

vhdl package signals modelsim wlf

I'm using Modelsim command line simulation & producing WLF of all signals. Language is VHDL. The problem is that, I've many signals defined in VHDL package, but those signals are not available in WLF after simulation is over. Is there any command or…

vhdl modelsim vlsi

asked Jun 18 '15 at 08:47

santhosh

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1 answer

Option & type_option in System Verilog

Coveegroup x; C: Coverpoint a {type_option.weight=0;} Endgroup I want to set coverpoint C weight to 0, for all the instances of covergroup x. So I have used type_option, as option is for instance specific settings. I have created 4 objects of…

verilog system-verilog vlsi

asked Mar 10 '15 at 15:46

Karan Shah

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Number of Prime Implicant and EPI

My TA solve this problem, Number of Prime Implicant (PI) for f(a,b,c,d)= Sigma m(0,2,4,5,8,10,11,13,15) is 7 and number of Essential PI (EPI) is 1. how this will be calculated? I think it's wrong. any idea? My solution is :

cpu-architecture digital-logic vlsi digital-design

asked Feb 23 '15 at 06:21

user4591951

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1 answer

What if I used Asynchronous reset, Should I have to make as synchronous turned it?

At we make IC( I mean physical design in Hardware). As i know, the input reset is always Asynchronous. I wonder that What if I used Asynchronous reset, Should I have to make into synchronous? or Can we just used asynchronous reset?

vlsi asic

asked Feb 07 '15 at 11:45

BONGKA

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