Can be a few supply1 nets in verilog code? If yes, what is the meaning?

Question

module inst();                                                                                                                                                                                                 
    supply1 sp1;
    supply1 sp2;
    top top1(.p1(sp1));
    top top2(.p1(sp2));
endmodule

Welcome to SO, please read [how to ask](https://stackoverflow.com/help/how-to-ask) and edit your question — Emmanuel-Lin, Jan 08 '19 at 14:07

score 1 · Answer 1 · answered Jan 08 '19 at 16:53

As far as digital logic is concerned, there is no difference between 5V supply and a 3.3V supply. But you may want to give them separate names for clarity, and you can also do simple low power simulations by forcing some of the supply1 nets to 0. You could not do that if you only delcared one supply1 net.

Can be a few supply1 nets in verilog code? If yes, what is the meaning?

1 Answers1