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I'm writing some test environment for practise but facing some strange issue. I have interface and made 2 modports for master and slave. But when I check the waveforms I see that when I change something in using master modports it takes additional clock cycle to be seen by slave modport. Same happens on the opposite side too.

Can you please explain why is that happening and what I have done wrong?

Here are portions of my code.

interface axi_if ();
    wire wready;
...

clocking m_cb @(posedge aclk);
default input #setup_time output #hold_time ;
  ...
  input   wready ;
  ...
endclocking: m_cb
 
clocking s_cb @(posedge aclk);
default input #setup_time output #hold_time ;
...
output wready ;
...
endclocking: c_cb
 

modport axi_master_modport(clocking m_cb, output aresetn);

modport axi_slave_modport( clocking s_cb, input aresetn);

endinterface

Thanks

Stepan Harutyunyan
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1 Answers1

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The modports are used to create different views of the same interface, just like in the example you gave, the same ports viewed from the perspective of the master or the slave.

But I noticed you are using clocking blocks. Clocking blocks are used to view the signals in a specific clock domain. And specially, inputs and outputs sampled at different moments as I explain here.

Bob
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  • Yes, I know that but here the problem is that with modports theres some strange 1 clock difference between modports. And Im using clocking blocks to drive/sample the data according to specific clock. – Stepan Harutyunyan Mar 19 '21 at 16:43
  • And what happens if you refer to the signals directly in the modport without the clock? – Bob Mar 21 '21 at 06:01