Questions tagged [uvm]

Universal Verification Methodology: SystemVerilog class library

From Wikipedia:
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM (eReuse Methodology) for the eVerification Language developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.

Related Resources

UVM User's Guide 1.1
UVM User's Guide 1.2
IEEE Std 1800.2-2017 (Universal Verification Methodology Language Reference Manual)

527 questions

votes

2 answers

How to monitor DUT outputs from a test/sequence?

I am a beginner in UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I…

verilog system-verilog uvm

asked Mar 28 '14 at 21:05

newbie

4,639
10
32
45

votes

1 answer

running UVM phases on multiple cores

How can we devote the individual phases in UVM like run, elaboration, build etc to run on multiple cores of the system. How can this be done through coding.

multithreading multicore uvm

asked Mar 10 '14 at 09:39

Deepti

votes

1 answer

Sequence item generating 'X' or unknown value

I have started a seq item on sequencer to generate seq item with random constraints but the item which is generated has many "X" values. What could be the reason behind this? Here is the code: virtual task run_phase(uvm_phase phase); begin …

system-verilog uvm

asked Mar 10 '14 at 05:57

user3383729

votes

1 answer

Driving input signals combinatorially (in the same cycle) in UVM

If I want to combinatorially drive a design input signal based on certain output from the design in UVM driver, what is the best way? If I implement it in run phase and look at the design output signal, I will see it on next positive edge of clock,…

verification system-verilog uvm

asked Jan 29 '14 at 03:19

user3242374

votes

2 answers

system verilog - uvm - wait for pkt in sequence

I'm running in system-verilog in uvm. I'm want to send a request in my sequence and to wait for a response pkt. how can i do it? Thanks for any help.

system-verilog uvm

asked Dec 25 '13 at 12:01

adir

1,257
2
16
22

votes

3 answers

Difference between scoreboard and checker

I have started developing a testbench for my RTL DUT. With all the components of the testbench, I want to implement self-checking mechanism for the verification of the functionality of the DUT. Hence, i need to develop scoreboard component. But…

verilog verification system-verilog register-transfer-level uvm

asked Nov 21 '13 at 07:14

Suhas

votes

1 answer

Integration of VIP developed in VMM into my UVM testbench

I have developed testbench using UVM methodology in system verilog for my whole system DUT. I have a VIP procured, which is in VMM methodology in system verilog. How do I integrate this VIP (in VMM) into my UVM testbench? Thanks.

verification system-verilog uvm

asked Nov 13 '13 at 09:33

Suhas

votes

1 answer

UVM Phase Query

I have couple of questions in relation with UVM phases build() and run(). They might be applicable to other verification methodologies as well a> Why is the build() phase executed in top-down order. Does this mean we need to new all the components…

system-verilog uvm

asked Oct 14 '13 at 03:27

venkstart

-1

votes

0 answers

Constraint for square sub matrices in a matrix

I have a 9x9 matrix as follows M[9][9] Each A,B,C etc below are sub square matrices of 3x3 so that its a total of 9x9 matrix. A B C M = D E F G H I I need to write a constraint for following…

matrix constraints system-verilog uvm

asked Aug 29 '23 at 09:19

Grace90

-1

votes

0 answers

What is a pipelined driver in AXI?

I know that AHB has a pipelined driver because it has two pipelined stages, address and data phase but I came across a question to write pipelined AXI3 driver in UVM somewhere, does it mean outstanding transactions ? and pipelined stages = no. of…

system-verilog uvm amba

asked Aug 23 '23 at 16:55

Grace90

-1

votes

2 answers

Turning off assertion fail comments

I'm writing assertions to detect a particular sequence occurrence. In case the sequence is not not true, I get prints in log for assertion failure. But I just want to check if sequence occurred or not. Is there any way to turn of these prints? FYI:…

system-verilog uvm system-verilog-assertions

asked Apr 20 '23 at 12:38

Rutuja14

-1

votes

1 answer

Gracefully terminating a virtual sequence by itself

I am looking for a way to gracefully end the task:body of a virtual sequence upon hitting a certain condition inside the same vseq body. ex: task my_vseq::body(); some logic; if (condition met) end of my_vseq some other…

sequence system-verilog uvm

asked Mar 15 '23 at 14:55

Shreerang Ajmire

-1

votes

2 answers

Sequence Item has null sequencer

I am writing a test which triggers the sequence on a valid sequencer but still facing issue as "Sequence Item has null sequencer". class gen_seq_item extends uvm_seqeuence_item; rand bit [WIDTH-1:0] generic_signal; …

system-verilog uvm

asked Sep 25 '22 at 18:45

Somesh

-1

votes

2 answers

Scoreboard in UVM

What do we do when we have to create a scoreboard for a certain design logic? For a memory I understand that we can compare the data written to DUT at a certain address to the data read at the same address. Suppose for a basic example of full adder…

verilog system-verilog uvm system-verilog-assertions vlsi

asked Mar 30 '22 at 05:31

Bunty Bhai

-1

votes

1 answer

How can I produce random single precision floating point numbers in systemverilog?

I'm trying to verify behavior of a floating point multiplier using Universal Verification Methodology and I have an issue. The problem is that when I want to generate single precision floating point numbers. Basically, This not possible directly and…

system-verilog uvm

asked Mar 07 '22 at 02:24

Nima Kolahimahmodi

Prev 1 2 3

…

35 36 Next