UVM task based phases - do the components must be sync'ed?

Question

task based phases - do the components must be sync'ed? meaning, can componentA be in reset_phase and componentB be in main_phase?

When using objections, that cannot be, right? The objections must be dropped before moving to the next phase. But when not raising objection, if I recall, if componentA complete its reset_phase and there is no objection protection, flow will move to the next phase and kill ALL other reset_phases in all components.

If that is so - how does the jump() in uvm_domain works - if componentA and componentB were in main_phase and componentA jumped to reset_phase - what will happen to each of the components (with and without objection protection)?

ADDITION: Here are several case - what will happen in each of them: Case 1)

• ComponentA has a counter to 100 (with 1cycle delay between each count) in main_phase
• ComponentB has a counter to 50 (with 1cycle delay between each count) in main_phase
• Both uvm_components above do not have raise_objection Once ComponentB reaches 50 -- what will happen?

Case 2)

• ComponentA has a counter to 100 (with 1cycle delay between each count) in main_phase
• ComponentB has a counter to 50 (with 1cycle delay between each count) in main_phase
• ComponentA has raise_objection - ComponentB do not Once ComponentB reaches 50 -- what will happen?

Answer 1

The UVM starts each task name_phase in order (run_phase, reset_phase, main_phase, ...) by concurrently calling the virtual method name_phase in every instance of a uvm_component. Unless you are doing user defined phases, (which I strongly recommend against doing) every component has a predefined set of phases that get called regardless of whether you have provided an override for that phase.

After forking of all of a particular phase in every component, the UVM waits for one delta cycle before waiting for an objection to that phase ending. That means if all your reset_phase methods in every component takes 100ns but none of them raise an objection, they all will be immediately terminated, and the process get repeated for the next phase (post_reset_phase). It is only the lack of objections to a phase that make the UVM move on to the next phase, not reaching the end of the any task.

When you can get phase jumping to work, it changes the next phase to execute, and then drops all the objections to the current phase.

The alternative to phase jumping and user defined phase domains is the proper use of sequences. This is much easier to communicate and makes it easier to integrate IP and not have to deal with different concepts of phasing.

Additional info:

Case 1) is what I mentioned above—both components terminate main_phase tasks immediately without getting to the next cycle.

Case 2) Reaching the the end of a task is not what terminates a phase, only when the last objection gets dropped. So both components will finish their main_phase tasks. If ComponentA does not drop its objections, the main_pase will get stuck not advancing to the next phase and eventually time-out after some predetermined time.