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I have started a seq item on sequencer to generate seq item with random constraints but the item which is generated has many "X" values. What could be the reason behind this?

Here is the code:

virtual task run_phase(uvm_phase phase);
begin
  uvm_test_done.raise_objection(this,"started sequence");
  `uvm_info(get_type_name(),"inside run_phase of base test:\n", UVM_LOW)
  fork
    #10;
    spi_m_seq.start(spi_env_inst.spi_master.spi_sequencer);
     #300;
  join
  uvm_test_done.drop_objection(this,"sequence finished");
end
endtask:run_phase
Greg
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user3383729
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  • It looks like you were able to get an answer, but in the future you should have a minimal code example in your question. In this case if you showed the definition of your sequence item and the driver code that creates the sequence item it would have helped. – nguthrie Mar 10 '14 at 11:43
  • HiHere is the code virtual task run_phase(uvm_phase phase); begin uvm_test_done.raise_objection(this,"started sequence"); `uvm_info(get_type_name(),"inside run_phase of base test:\n", UVM_LOW) fork #10; spi_m_seq.start(spi_env_inst.spi_master.spi_sequencer); #300; join uvm_test_done.drop_objection(this,"sequence finished"); end endtask:run_phase – user3383729 Mar 10 '14 at 12:47

1 Answers1

2

The SystemVerilog LRM states that the constraint solve can only handle 2-value logic. This means that any X's you have are due to uninitialized 4-state logic types in your class. Here's and example of what I mean:

package some_package;

  class some_class;
    rand logic[15:0] field1;
         logic[15:0] field2;

    function void print();
      $display("field1 = %x", field1);
      $display("field2 = %x", field2);
    endfunction
  endclass
endpackage

module top;
  import some_package::*;

  initial begin
    some_class my_obj = new();
    my_obj.randomize();
    my_obj.print();
  end

endmodule

In the example above, both fields are of type logic (4-state), but only field1 is declared as rand. This means that when my_obj is randomized, only this field will be assigned by the constraint solver. The value of field2 will remain 16'bx (the initial value of 4-state types).

Tudor Timi
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  • Yeah i have declared it as "rand logic [15:0] data;" only..after i do uvm_create(req);uvm_send(req) but it is assigning with the value 'h0XXXX – user3383729 Mar 10 '14 at 09:45
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    `uvm_create` and `uvm_send` don't call `randomize()`. `uvm_do` does. Or, what would be even better would be not using the macros at all and implementing the driver-sequencer handshake in your own code. There's a question about that here: http://stackoverflow.com/questions/22255018/how-to-perform-uvm-do-on-without-randomization/22257569#22257569 – Tudor Timi Mar 10 '14 at 10:25