`include "top.v"
`include "c_top.v"
module fixture;
reg [31:0]F[0:100];
reg [31:0]F2[0:50];
reg [31:0]F3[0:50];
reg [31:0]a,b;
reg clk,reset,s;
wire [31:0]r_expected,r_actual;
wire exception_expected,exception_actual;
integer i;
integer j=32;
integer k;
integer m,u;
topdut t1(a,b,s,clk,reset,r_actual,exception_actual);
c_toptest t2(a,b,s,clk,reset,r_expected,exception_expected);
initial
begin
clk = 1'b1;
forever #10 clk = ~clk;
end
//initial
//$monitor($time,"clk=%b reset =%b a=%h b=%h s=%b exception=%b r=%h ",clk,reset,a,b,s,exception,r);
integer ab;
initial
begin
ab=$fopen("input_ab.txt","w");
for(i=0;i<100;i=i+1)
begin
$fdisplay(ab,"%b",$random());
end
$fclose(ab);
end
initial
begin
$readmemb("input_ab.txt",F);
end
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
a <= 32'b0;
b <= 32'b0;
k <= 0;
m <=0;
u <=0;
end
else
begin
a <= F[k];
b <= F[k+50];
k <= k+1;
$display("r is %b and m is %i",r_expected,m);
F2[m] <= r_expected;
m <= m+1;
if(k>=29)
begin
F3[u] <= r_actual;
u <= u+1;
end
end
end
initial
begin
for(i=0;i<100;i = i+1)
begin
$display("c%b c2%b a%b b%b",F2[i],F3[i],F[i],F[i+50]);
end
end
initial
begin
// Initialize Inputs
reset = 1'b0;
#30
reset = 1'b1;
s = 1'b0;
end
initial
begin
#1500 $finish;
end
endmodule
When I display F2[] and F3[] it is taking xxxxxxx. Even though m and r are having valid values.
Please suggest some solution. I know there is a small glitch here.
I guess all my declarations are correct.
All my modules are giving correct output from DUT. Only in this testbench something is wrong
