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Variables in testbench mostly are instantiated as bit rather than reg. But bit is just 2 state variable (0 and 1), reg is 4 state variable (0,1,x and z). Why people used bit as testbench variables? I took over an old project and all the testbench variables were bit. So when the checker perform checks like

if (data_rtl === data_expected) // reg[63:0] data_rtl, bit[63:0] data_expected

I couldn't perform X check on the data_expected side. Certainly it's common to use bit, why people are doing this? What's the advantage of bit over reg in systemverilog ?

TyL
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3 Answers3

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Generally, there no need for 4-state types in the stimulus generation and prediction components of your testbench. Two-state simulation has the benefit of less memory overhead, which effectively doubles the size of your data caches. You basically just need to check for X's at the proper time in the interface between the testbench and DUT. The generation and propagation of X's in a design is a broad topic in itself. Most simulations are grossly inaccurate in either being too optimistic or too pessimistic when it comes to X's in different areas of your design. Sometimes, it's better to use static analysis (timing or formal) tools in these situation.

dave_59
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  • _Most simulations are grossly inaccurate in either being too optimistic or too pessimistic when it comes to X's in different areas of your design. _ too pessimistic wasn't too bad is it? Is that one of the reason we use X rather than random values? – TyL May 05 '16 at 16:52
  • It depends if those X's are preventing you from making progress in your simulation. For example, sometimes an X will propagate into an FSM and the states will go X even though in real hardware that will never happen. – dave_59 May 05 '16 at 17:23
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To a certain extent you answered your own question. bit is a two-state variable. For a lot of verification testbench applications, x and z values are not necessary. The computational/memory overhead of the extra two states, as well as the additional concern about the possibility of the variable being set to z, or x, aren't needed, and so aren't used.

dolphus333
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There are some a key difference in bit & reg

  • reg is a 4 State Variable (1 or 0 or X or Z, with default X), but bit is a 2 State Variable (0 or 1, with default 0)

Now what does that effect to us.

  • 4 State variables, are necessary for hardware, as in hardware, depending upon voltage level & driver of a wire, a wire can have logical value 1 or 0 or X or Z. So for hardware point of view, reg should be used.

  • But for stimulus point of view, often we do not require X or Z state, as you would never drive a wire with unknown (X), or without any driver (Z). So in that case, bit can be used, as bit contains only 2 states.

Hope you would have got the difference

Karan Shah
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  • I slight disagree you about stimulus point of view, sometimes we need to test DUT can do X-propagation. If the stimulus variable can hold X, it would easier to write a consistent BFM rather than driving DUT differently based on if a X is required on DUT interface. – TyL May 05 '16 at 16:47
  • @TyL : Yes, in real scenario, every DUT will be connected to another design and so another design (which is driver of the dut) may have output x or may not drive op (z). So BFM must be used to mimick it. I was talking about independent manual driver in answer. – Karan Shah May 06 '16 at 07:34