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Basically, I have a system verilog design that I need to integrate in a simulation framework that's in verilog. So I need to create a wrapper in order to interface with the DUT but am having issues trying to do so.

The interface to the DUT has an interface block as well as other inputs and outputs. The interface to the DUT is seen below

interface ifc(input clk, input rst);
    logic [`DATA_WIDTH-1:0] data;
    logic                   valid;
    modport in(
        input data,
        input valid
    )
    modport out(
        output data,
        output valid
    )
endinterface

The DUT uses the interface as such

module DUT(
    ifc.in  in0,
    ifc.in  in1,
    ifc.out out0,
    ifc.out out1,

    output error);

    ....

endmodule

I created an instance of the interface block and assigned the corresponding signals to the interface and passed the interface into the DUT. 

module sim(input clk, input rst, 
           input in0, input in1, 
           input ivalid0, input ivalid1,
           output out0, output out1
           output ovalid0, output ovalid1 );

    ifc if0(.clk(clk), .rst(rst));
    ifc if1(.clk(clk), .rst(rst));

    assign if0.data = in0;
    assign if1.data = in1;

    assign if0.valid = ivalid0;
    assign if1.valid = ivalid1;

    assign out0 = if0.data;
    assign out1 = if1.data;

    assign ovalid0 = if0.valid ;
    assign ovalid1 = if1.valid ;

    DUT dut(
        .in0(if0.in),
        .in1(if1.in),
        .out0(if0.out),
        .out1(if1.out)
    );
endmodule

When I try and simulate in Modelsim, I get an error that This or another usage of 'if0.in' inconsistent with 'modport' object. In all the examples I have seen, they use a SystemVerilog wrapper for a Verilog DUT, but I have not seen any the other way around. Is it even possible to do it the other way around? How would I go about instantiating a systemverilog module with an interface in a Verilog wrapper.

Thanks for any help.

okebz
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  • Does the error message point to a specific line? Your code compiles fine for me after fixing all your typos (missing ,'s and ;'s). Perhaps you missed something important when you transcribed your code. – dave_59 Jun 03 '16 at 22:53
  • It compiles fine, but when I start simulation, it gives me that error message. It points to the line the .in0(if0.in) line when i instantiate the DUT. – okebz Jun 03 '16 at 23:38
  • Doesn't do that for me. Please edit your example to be self contained and runnable – dave_59 Jun 04 '16 at 01:57
  • With the given code, `in0` and `out0` are sharing the same interface instacne. Both modports access the same variables, therefore there are multiple drivers on `if0.data` (from the modeport `out0` and the assign statement) – Greg Jun 04 '16 at 21:18
  • So I created two more interfaces and separated to input and output interface, and assigned it appropriately. I am still getting the same error saying that "this or another usage of 'if0.in' inconsistent with 'modport' object". – okebz Jun 06 '16 at 17:02
  • I fixed the problem. The problem was that the wrapper was in verilog. And interface is only used in system verilog so when I tried to instantiate the interface in the verilog file, it complains. I just changed the verilog extension to system verilog and eveything went through fine. – okebz Jun 08 '16 at 18:53

1 Answers1

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Your DUT instantiation is incorrect syntax. When you instantiate a module with interfaces, you just connect the interface. You don't include the modport. Try this:

DUT dut(
    .in0(if0),
    .in1(if1),
    .out0(if0),
    .out1(if1)
);
J. R. Petrus
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