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In IEEE 1800-2005 or later, what is the difference between & and && binary operators? Are they equivalent?

I noticed that these coverpoint definitions behave identically where a and b are of type bit:

  • cp: coverpoint a & b;
  • cp: coverpoint a && b;
Victor Lyuboslavsky
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2 Answers2

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&& is a boolean operator which we call "logical AND". This doesn't mean that it must operate on boolean operands, but that its return type is boolean. In SV, boolean means:

1'b1 \\ true
1'b0 \\ false
1'bx \\ undef

When logical AND operates on single bit operands the result is obvious, but the issue arises when it operates on a vector. For example:

logic [1:0] vector;
...
vector = 2'b10;
if (1'b1 && vector) ...

For purpose of this logical operation, vector is tested for equality to 0. If it is, then its boolean value is defined as "false", otherwise "true". In the above example, the result is "true".

& is a bitwise AND and reduction AND operators. Whether it is executed as bitwise or reduction is determined by the context:

logic [1:0] vector1;
logic [1:0] vector2;
logic [1:0] vector3;
...
vector1 = 2'b10;
vector2 = 2'b01;
...
vector3 = vector2 & vector1; // bitwise; vector3 = 2'b00
if ( (&vector1) || (&vector2) ) ... // reduction; the result of each reduction is 1'b0

Bitwise operator performs logical AND operation on each pair of corresponding bits of operands. The result is a vector which width equals to maximal width of operands.

Reduction operator performs logical AND operation between all the bits of a single vector. The result is a single bit boolean value.

NOTE: when executed on a single bit operands, the results of bitwise and logical operators are the same. However, when even one of the operands is a vector, the results may differ.

Vasiliy
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  • This isn't quite correct. In Verilog, a vector (or any other) object is 'true' if it is non-zero, *and* it is known - in other words, it does not contain x/z metavalues. So, it's not 'tested for equality to 0'. @VL: try not to combine Verilog and SV questions - they're different languages. You wouldn't ask a C question in a C++ group, or vice-versa. – EML Jun 27 '13 at 07:51
  • @EML, I mentioned that there is "undef" outcome for logical operations, but I didn't want to go into explanations because it is not the point of the question. Anyhow, I do think that the way it works is testing for equality to 0 and assigning "true" otherwise. It is kind of obvious that if the vector contains X's or Z's the result of logical operation is not reliable (unless special operators are used). BTW, I am not aware of difference in behavior of these operators between Verilog and SV. What are they? – Vasiliy Jun 27 '13 at 08:14
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    there's no actual definition of 'true' in Verilog (don't know about SV). `if(2'b0x)` takes the false path, and `if(2'b1x)` takes the true path. The key is to do a reduction OR of a vector operand and see what the resulting 1-bit value would do in the same situation. So, your example of `(1'b1 && vector)` is equivalent to `(1'b1 & (|vector))`. If you look at it this way, you can see that `vector` isn't tested for equality to 0. `(1'b1 && 2'b0x)` returns `1'bx`, while `(1'b1 && 2'b1x)` returns `1'b1`. The vector is non-zero in both cases, but the result differs. – EML Jul 15 '13 at 08:36
  • Further to above - IMO, 'tested for equality to 0' would be a more logical way to do it, and a better extension from two-state logic, but that's not how Verilog does it. I've got no idea what, if anything, SV has changed, but it's still a different language. – EML Jul 15 '13 at 08:39
  • @EML "no definition of true". Hmmm, IEEE 1364-2005 section 5.1.9 "Logical Operators": "The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false)..." – gwideman Feb 26 '18 at 09:08
  • @gwideman - '1' may be defined as true, but what about 2? or 2'b0x? Unfortunately, the LRM was constructed over years on an ad-hoc basis, starting as a definition (incomplete and incorrect) of what one commercial simulator (XL) did, and never got to the level of clarity you'd expect in a mainstream language. The SV LRM may be better, but I'd be surprised. – EML Feb 26 '18 at 09:41
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&& is logical AND. It accepts two booleans and returns boolean.

& is bitwise AND. It accepts two numbers and returns a number.

In the above example, the behavior would be different if a and b where both packed bit [1:0].

Victor Lyuboslavsky
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