Arithmetic shift acts as a logical shift, regardless of the signed variable

Question

I've got a register declared as so:

logic signed [15:0][2:0][15:0] registers;

When I place a 2's compliment number into the array and arithmetically shift the number, it logical shifts instead:

registers[0][0] = 16'b1000000000000000;
registers[0][0] = registers[0][0]>>>2;

Apparently, the system will logical shift instead of arithmetically shift if the number is not signed. However as you can clearly see, 'registers' is definitely signed.

Does anybody know what I might be missing here?

Thanks!

score 13 · Accepted Answer · answered Jan 07 '13 at 13:50

13

With Verilog, once you take a part-select, the result is unsigned. Use the $signed system task on the part select to make it signed.

res = $signed(registers[0][0]) >>> 2;

answered Jan 07 '13 at 13:50

Marty

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Is this synthesible? Is there another way to do this? – Parth K Sep 08 '18 at 16:08
In SystemVerilog, you can also use a cast `res = signed'(registers[0][0]) >>> 2;` Both should be synthesizable – dave_59 Sep 08 '18 at 18:35
for me, it just worked as follows: `res = $signed(registers[0][0] >>> 2);` – Delfino Apr 12 '21 at 00:05

Arithmetic shift acts as a logical shift, regardless of the signed variable

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