I am writing a systemverilog module and I need to make sure that a certain macro is set to allow compilation to proceed.
I have tried the below, but it simply gives the syntax error "unexpected SYSTEM_IDENTIFIER" $fatal.
I know that does technically stop the compilation, but does anyone know of a more graceful solution?
* Correction, if the syntax in the `else branch is not correct, none of the branches will compile successfully.
`ifdef MACRO_0
// Some code
`elsif MACRO_1
// Some other code
`else
$fatal("MACRO_0 or MACRO_1 must be set for compilation");
`endif
As per recommendation, adding the below information to the question:
The code is in a module but not inside an initial or always statement. I am hoping to find a solution that will allow me to terminate the compilation i.e. elaboration of hdl. I am designing for FPGA implementation and I need to make sure that no other user of this code can reach the synthesis phase of a design flow without setting one of these macros.