Can I synthesize a parameterized function in systemverilog where structure is used as a parameter?

Question

I was trying to synthesize a parameterized function where a structure is given as a parameter. I get the following error in the beginning of the parameterized function "Syntax error at or near token 'virtual'."

I was trying to compile this simple package.

   package def;

typedef struct packed {
    logic[10:0] SIZE1;
    logic[10:0] SIZE2;
} my_struct;
endpackage


import def::*;

virtual class my_class #(parameter my_struct new_struct = '{10,11});
static function [new_struct.SIZE2-1:0] adder (input [new_struct.SIZE1-1:0] a, b);
return a+b; 
endfunction
endclass

module top 
#(parameter my_struct new_struct2 = '{63,64})
(input logic [new_struct2.SIZE1-1:0] a, b,
output logic [new_struct2.SIZE2-1:0] y) ;
assign y = my_class #(.new_struct(new_struct2))::adder(a,b); 
endmodule

Am I doing something wrong? Or this feature is not supported in Synopsys DC?

(Update: The code has been updated, this one can be synthesized with Synopsys DC)

Answer 1

According to http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf § 5.6.7 Parametrized task/function arguments using static classes, the class must be virtual and defined in the $unit declaration space. This means the class cannot be defined inside a package. It is a weird requirements, as the paper points out.

Try moving the class out of the package. You could also try importing the function the the $unit scope, but not sure is this will work.

...
endpackage : def
import def::my_class; // or def::*;
...