Why do we use Blocking statement in Combinatorial Circuits designed using Always Block in Verilog/Systemverilog ? Why not Nonblocking?

Question

Everywhere it is mentioned this as a guideline, but after lot of thought i want to know what harm will it cause if we use Nonblocking statement inside Always Block for Combinatorial also. I won't be mixing the two together. But what i feel is when we use Nonblocking for Combinatorial statements in Always Block it represents the hardware more accurately. Does it not...?

For Example, if we take the following circuit: Small sample circuit diagram

In this diagram when the inputs a,b,c are supplied the outputs x1 and x will not be available instantly. There will be gate delays. first x1 will be available and then x will be available. If we use blocking statements both are available instantly. If we use nonblocking, it resembles the hardware more accurately.

For Example, if we take the following code based on the above diagram

module block_nonblock(output logic x,x1,y,y1,input logic a,b,c);

always@* begin : BLOCKING
    x1 = a & b;
    x  = x1 & c; 
end

always@* begin : NONBLOCKING
    y1 <= a & b;
    y  <= y1 & c; 
end

endmodule

This synthesizes as: RTL Diagram of Non Blocking and Blocking Code

Both are synthesized as And gates, and give same simulation results but when we check for the changes in output in delta time, i feel the Non blocking matches the hardware more accurately as compared to the Blocking.

Also i went through : IEEE P1364.1 / D1.6 Draft Standard for Verilog® Register Transfer Level Synthesis, which specifies the use of non blocking for Sequential modeling but doesn't specify specifically using blocking for Combinational modeling using Always Block. It says don't mix the two(Blocking and Nonblocking) in Combinational statements.

So, shouldn't we use nonblocking for combinational statements in always blocks which are dealing with pure combi logic (non sequential/ no clocks involved)

Related [Question & Answer](http://electronics.stackexchange.com/a/222797/13513) — Morgan, Mar 30 '16 at 13:34
NB: The latest standard is (free) [SystemVerilog IEEE 1800-2012 Standard](http://standards.ieee.org/getieee/1800/download/1800-2012.pdf). — Morgan, Mar 30 '16 at 13:37

score 5 · Answer 1 · answered Mar 30 '16 at 12:47

The harm is in simulation; in performance, and in race conditions.

Your NONBLOCKING code executes twice for every change in a or b. Non-blocking assignment updates are scheduled into a later queue of events, and this causes a much bigger rippling effect where blocks get repeatedly executed.

When you simulate RTL code, you are doing so in the absence of physical delays and synthesis tools understand how the logic is going to be implemented. But simulation tools cannot do this and also need to work with non-synthesizable code. They have to execute the code exactly as written. And they also have to deal with massive amounts of concurrency executing code on a processor with a single or limited number of threads. So simulation introduces race condition in software that would not exist in real hardware. Non-blocking assignments are there to prevent those race conditions when writing sequential logic. But they can have the opposite affect if you use them in combinational logic, especially when used in the combinational logic involved in the generation of clocks.

I understand the importance of nonblocking in sequential statements (i.e with clock involved). in the above circuit (the one in the beginning) if we provide all inputs simultaneously, then practically we wont get the EXPECTED CORRECT value at X1 and X at the same time(coz of gate delays). First we get X1 and that very instant if we check X it will have something else (not the expected correct value). In the nxt step i.e. after the gate delay of the 2nd AND gate we gt the Correct expected value at X. So, isnt this best described by nonblocking.? Jus tryin to find an ans that'll convince me. :-) — Edwin Joseph, Mar 31 '16 at 05:12
When you write RTL code, you are supposed to be looking at the functional aspects of what you are trying to specify, not its its gate-level representation. You can't always assume the RTL statements you write will always correspond 1-for-1 with the gate-level representation. So to expect RTL to ripple out in the exact manner that it would to at the gate-level is not appropriate. — dave_59, Mar 31 '16 at 11:15

Matthew Taylor · Answer 2 · 2016-03-30T15:26:05.477

1

You ask "So, shouldn't we use nonblocking for combinational statemnts in Sequential?" The answer is No.

If you use non-blocking assignments for combinational logic in clocked always blocks, you will get more flip-flops than you expect. Basically, non-blocking assignments in clocked always blocks will behave like flip-flops when you simulate and infer flip-flops when you synthesise.

So,

1 - use blocking assignments for gates and

2 - use non-blocking assignments for flip-flops.

edited Mar 30 '16 at 15:26

answered Mar 30 '16 at 12:29

Matthew Taylor

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Sorry.. What i meant was "So, shouldn't we use nonblocking for combinational statements in always blocks which are dealing with pure combi logic (non sequential/ no clocks involved)" – Edwin Joseph Mar 31 '16 at 04:31

score 1 · Answer 3 · answered Mar 30 '16 at 16:27

Your very own description of the behaviour of the circuit suggest actually the use of blocking operations.

You say: (emphasys mine)

In this diagram when the inputs a,b,c are supplied the outputs x1 and x will not be available instantly. There will be gate delays. first x1 will be available and then x will be available. If we use blocking statements both are available instantly. If we use nonblocking, it resembles the hardware more accurately.

So you need x1 to be available before x. So your always block must use a blocking assignment, so...

always@* begin : BLOCKING
    x1 = a & b;
    x  = x1 & c; 
end

x1 first will have a known value, and then, and only then, x will have a value. If you use non blocking...

always@* begin : NON BLOCKING
    x1 <= a & b;
    x  <= x1 & c; 
end

You are telling the simulator that x1 and x will be evaluated at the same time.

Although for synthesis this may work, in simulation this won't, and you want to make sure your simulated circuit works as intended before going over the synthesis phase.

I understand what you are saying, but my intent is to write a code which best describes the above circuit. If i use blocking statements, will it resemble the hardware more accurately (since, the correct value of X1 will be ascertained first and then the value of X would follwo after that).OR. if use non blocking statements, it doesnt wait for X1 to have the correct value and then assign X. It directly gives me the value as is(as though we had actual wires connected between the gates). I am just trying to find an answer that will convince me. — Edwin Joseph, Mar 31 '16 at 05:00

score 0 · Answer 4 · answered Apr 12 '16 at 12:05

We should not use non-blocking assignments in Combinational block, because if we use non-blocking it will infer the transport delays in the design due to this our results will never come what we expected, but if we use blocking , this blocking will able to suppress the transport delays in the design and we can safely said that there is no glitches in the waveform. So it is recommended that we should use blocking statements in combinational designs.

Edwin Joseph · Answer 5 · 2016-04-06T05:03:51.813

I have found a satisfactory answer and need input for it. I feel we should use Nonblocking statements for both combinational and sequential statements.

For sequential it is pretty clear y we should use.

I will describe the reason for Combi Blocks. For combinational segments we will use Nonblocking Statements because, when we use Blocking or NonBlocking statements, even though it gives us the same hardware or RTL in the end; it is the nonblocking statements which shows us the glitches in simulation. Theses glitches will be there in hardware as well (because of Gate Delays), so we can rectify them when we see them in Simulation so that they will cause less harm at a later stage of the design/development cycle.

In the circuit I originally mentioned in the question if we give the inputs together as (A = 1,B = 1,C = 0) and then change them together after say 10ns as (A=1,B=0,C=1) then we can see that there is a glitch. This glitch will be there in actual Hardware as well. But this is only shown in simulation by Nonblocking Statements Output (Y) and not by Blocking Statements Output (X). Once we see a glitch we van take additional measures to prevent this from happening, so that it doesnt happen in hardware.

Hence i feel it is safe to conclude that we must use Nonblocking statements for combi blocks.

Why do we use Blocking statement in Combinatorial Circuits designed using Always Block in Verilog/Systemverilog ? Why not Nonblocking?

5 Answers5