Logic synthesis from an arbitary piece of code

Question

I have completed on a project making physical logic gates and am now looking for a way to turn an arbitrary program into some series of logic gates so I can use them.

I need a program that can take some arbitrary function (say f= x^2 -1) directly into some series of logic gates. Does this already exist?

I have found Verilog and several other open source options but they do not appear to output circuit diagrams. There is also Quartus II and other programs which will convert VHDL code into a schematic.

Preferably I would like something that compiles Python/C++ to a logic gate schematic directly - but really any language is fine.

Thanks.

EDIT: I do mean physical gates - they use ball bearings!

I have all of the 1-bit-input/1-bit-output gates and all of the 2-bit-input/1-bit output-gates. From these I can also construct a MAJ gate to do error correction.

So you simply want a converter: Python/C++ -> Verilog/VHDL? You should take a look e.g. at Vivado High-Level Synthesis tool. — Qiu, Jun 03 '15 at 08:40
See also http://en.m.wikipedia.org/wiki/High-level_synthesis for other options. — wilcroft, Jun 03 '15 at 18:43
Thanks - ideally what Im looking for would take Python/C++ -> Verilog/VHDL -> A schematic diagram of logic gates. — Josh Ketts, Jun 04 '15 at 09:31

score 4 · Accepted Answer · 2022-01-06T13:34:57.293

Write your arbitrary code in VHDL, turning VHDL into gates is what a synthesis tool does.

Not everything you write will be synthesisable; file handling can't be translated into gates, neither can anything that conventionally uses the heap (such as malloc, or pointers, in C, or "new" and access types in VHDL). Floating point can be synthesised (with VHDL-2008) but it's not quite as simple as signal A : Real; A <= 2.0 * X * X - 1.0; you have to use types from the synthesisable floating point library. So there may be some negotiation with the tool about the programming language subset you can use.

But I'm sensing a slightly different question here : how do I translate arbitrary code into MY logic gates, implemented in (technology not described in the question). And that's harder to answer.

Synthesis tools usually come from a vendor such as an FPGA vendor, and they translate arbitrary code into that vendor's logic gates, not yours.

The ideal solution is to create a library describing your logic technology, which plugs into a vendor-neutral synthesis tool, such as Synplicity from Synopsys. Then Synplicity can synthesise to your technology instead of an FPGA vendor's.

OK, but creating that library is likely to be a task roughly on a par with writing a backend for a custom CPU's instruction set, and integrating that backend into gcc. Except that Synplicity, unlike gcc, isn't open source, so without considerable financial and technical resources, and help and internal documentation from a major EDA tool company, it's approximately impossible. (At this point I'd be delighted to be corrected by someone who's actually done it)

EDIT (nearly 7 years later!)

GHDL (open source VHDL simulator) available from Github has grown a synthesis branch, so this route is now likely to be easier (I'll stop short of saying easy!) or may be a better choice than a proprietary toolset for the route below. It has a tie-in to the YOSYS open source synthesis suite. CAVEAT : I haven't tried it, but it may be worth a look for future viewers of this question.

(end edit)

So we need a different approach.

Back to the FPGA synth tools : I'll use Xilinx XST as an example. It'll synth to Xilinx primitives, in some Xilinx closed internal format.

However there's also an option labelled "Write post-synthesis netlist".

Using that, you can get a structural VHDL file representing the translation of your arbitrary code into Xilinx gates, flip-flops, and other elements, which are drawn from the Simprims library.

Attempt to compile that (e.g. in a simulator) without making the Simprims library visible (e.g. with the library Simprims; use Simprims; statements commented out and you'll get something valuable:

a list of compilation errors

Not so valuable, you may think : except that it's actually a list of gates, flipflops and other elements that are needed to implement your design.

If you can find (or create) a one-to-one correspondence between these, and elements in your chosen technology, then you can map this netlist to your technology.

If there are Simprims elements for which you don't have equivalents, you need to implement them - e.g. by creating 3-input AND gates from networks of the 2-input NAND gates you have.

Use the corresponding elements from your own (VHDL) library, instead of Simprims, and you should, in theory, have a usable compiled design.

(You're on your own with problems like layout, routing, timing analysis. This is not trivial, but for the sake of this question I'm assuming your "project making physical gates" has these covered...)

Thankyou for the great response! This should solve the problem. — Josh Ketts, Jun 04 '15 at 09:55
Neat! Then this approach is as close as you're going to get. Note that Xilinx tools target a variety of different devices, you may find targetting a simpler device might reduce the list of needed primitives (components from the Simprims library).Or you may want to try Actel/Microsemi tools (Libero, which uses Synplicity) Their FPGAs such as ProAsic 3 have simpler internals. — , Jun 04 '15 at 09:55
You may have to reduce your ambitions : I suspect 4-bit addition would be stretching ball-bearing technology far enough to start with! Also, Xilinx uses architectural tricks to simplify arithmetic : unless you have ball-bearing fast carry chains, simpler FPGA technologies (Microsemi) probably fit better. — , Jun 04 '15 at 10:01

score 1 · Answer 2 · answered Mar 04 '20 at 23:16

Firstly, logic synthesis is basic logic optimization of logic circuits, or the transformation of structural logic circuits into a data structure representing logic circuits. See https://stackoverflow.com/a/60535990/1531728 for resources about logic synthesis.

Secondly, to transform computer programs (e.g., in Python, C, C++, or otherwise) into logic circuits, you would need to perform high-level synthesis (or behavioral synthesis) to transform the computer program by parsing it into a control and data flow graph (CDFG, or a pair of control flow graph and a dataflow graph), optimize the CDFG, and subsequently transform this CDFG into a logic circuit for logic synthesis. Once you have the logic circuit, you still need to perform physical design (e.g., floorplanning, placement, and routing) to map that logic circuit into a layout for tapeout (standard-cell -based digital integrated circuit design) or onto a field-programmable gate array (FPGA).

The references below provide literature reviews into the topics I mentioned.

@book{Lavagno2016a,
    Address = {Boca Raton, {FL}},
    Author = {Luciano Lavagno and Igor L. Markov and Grant Martin and Louis K. Scheffer},
    Doi = {https://dx.doi.org/10.1201/b19569},
    Edition = {Second},
    Publisher = {{CRC} Press},
    Series = {Electronic Design Automation for Integrated Circuits Handbook},
    Title = {Electronic Design Automation for {IC} System Design, Verification, and Testing},
    Volume = {1},
    Year = {2016}}

@book{Lavagno2016,
    Address = {Boca Raton, {FL}},
    Author = {Luciano Lavagno and Igor L. Markov and Grant Martin and Louis K. Scheffer},
    Doi = {https://dx.doi.org/10.1201/b19714},
    Edition = {Second},
    Publisher = {{CRC} Press},
    Series = {Electronic Design Automation for Integrated Circuits Handbook},
    Title = {Electronic Design Automation for {IC} Implementation, Circuit Design, and Process Technology},
    Volume = {2},
    Year = {2016}}

See https://github.com/lsils/lstools-showcase for the state-of-the-art logic synthesis libraries from EPFL (Ecole Polytechnique Fédérale de Lausanne) in Lausanne, Switzerland.

You can use these tools to perform logic synthesis. They are programs, commercial high-level synthesis software, that transform C or C++ code into Verilog (or some other hardware description language, HDL), and subsequently into logic circuits.

You can also consider Python-based HDL (such as PyMTL, PyRTL, or MyHDL), Scala-based HDL (e.g., Chisel HDL), or Haskell-based HDL (e.g., Clash). These HDLs provide a workaround to your goal of transforming computer programs into logic circuits.

Logic synthesis from an arbitary piece of code

2 Answers2