Highest Voted 'synthesis' Questions

3

votes

1 answer

How to make the data_flow control of a matrix multiplier synthesizable?

I have designed a matrix-vector multiplier with systolic array architecture. I finally got the simulation to work. Now that I want to synthesize the design it seems that the data_flow control block is not synthesizable (the always block). And I…

verilog system-verilog synthesis

asked Mar 29 '23 at 19:00

engineer1155

36
13

3

votes

4 answers

Silverlight and audio synthesis

is it at all possible to generate sound on-the-fly in a Silverlight app and play it? I.e. if I want to play a sine-wave, can I generate a buffer and feed it to some media API? Cheers Nik

silverlight audio synthesis

asked Mar 24 '09 at 11:31

niklassaers

8,480
20
99
146

3

votes

1 answer

Loop iteration limit exceeded in synthesis but not in simulation

I wrote code in verilog that cycles through active channels. The idea is to skip channels that are marked by 0 in the activity vector. I tested the code in a simulator screen shot from simulatior, it works and performs as expected. When I try to…

verilog fpga synthesis

asked Mar 16 '19 at 21:57

Alexander Tarnavsky

103
7

3

votes

1 answer

understanding a binary multiplier using gate-level diagram

I am having problem understanding the following code (bimpy.v) that does unsigned 2-bit multiply operation. Edit: Added comment from one of my friend: the following modification does the same thing with fewer logic !! o_r <= (i_a[0] ? i_b : 2'b0) +…

binary verilog fpga multiplication synthesis

asked Jan 18 '19 at 04:21

kevin998x

899
2
10
23

3

votes

1 answer

If-statements in VHDL: nested vs. multiple conditions

here is what my code somewhat looks like... (I know it does't compile, it's just pseudo code.) signal lowBound : std_logic_vector(15 downto 0); signal highBound : std_logic_vector(15 downto 0); signal result_01 : …

if-statement vhdl fpga timing synthesis

asked Dec 11 '18 at 10:21

matzeBurger

33
1
5

3

votes

0 answers

What is the difference between using a 'constant' and using a number in vhdl

As part of adaptations to an existing large design on Artix-7 FPGA, I implemented a simple counting mechanism, something similar to "Archticture with 'constant' ", so that in the future, I can just change the value of the constant and not worry too…

vhdl fpga synthesis vivado

asked Sep 06 '17 at 11:30

Vinay Madapura

327
5
17

3

votes

1 answer

VHDL Warning Xst:1293 FF/Latch has a constant value of 0

None of the answer on the internet worked for me as I am a beginner in VHDL. I am making a password interface in vhdl with pushbuttons and LEDs. My program simulates correctly as expected. Basically, I want LEDs to blink when entering wrong…

warnings vhdl xilinx synthesis xilinx-ise

asked Aug 11 '17 at 15:43

Pankaj Kumar

131
12

3

votes

1 answer

Query for VHDL synthesis for IC Design (Not FPGA), specifically in case of variable assignment

If for a given process, I declare a variable (let's say a 1 bit variable, variable temp : std_logic;) then can I assign a value to the variable if a given condition returns true, i.e. if (xyz=1) then --Assuming that this condition returns…

vhdl synthesis register-transfer-level asic soc

asked Apr 22 '17 at 13:43

Gaurav Singh

127
9

3

votes

5 answers

Efficient synthesis of a 4-to-1 function in Verilog

I need to implement a 4-to-1 function in Veriog. The input is 4 bits, a number from 0-15. The output is a single bit, 0 or 1. Each input gives a different output and the mapping from inputs to outputs is known, but the inputs and outputs…

logic verilog synthesis version-control

asked Sep 03 '08 at 22:02

Eyal

5,728
7
43
70

3

votes

1 answer

What is "net" in HDL synthesis

I am a beginner in circuit synthesis, and I came across the word net a lot, but I am never able to find its standard definition. It seems to me that it refers to any kind of "black box" where it receives inputs and produce outputs. So it can be a…

verilog hdl synthesis

asked Mar 03 '17 at 10:24

xtt

857
1
8
24

3

votes

2 answers

Synthesis global instance count

I couldn't find any questions related to this, but it is possible that I just don't know what to search for. When using a synthesis tool (let's say Synplify if you need a specific tool but it would be best if there were a standard compliant version…

vhdl verilog hdl synthesis

asked Feb 01 '17 at 19:29

hops

231
4
12

3

votes

1 answer

Is there a system verilog task which returns the length of a reg / logic?

It would be nice to have something similar to sizeof() from C. Needless to mention I don't expect it to be synthesizeable.

verilog fpga system-verilog synthesis

asked Mar 27 '16 at 02:05

Jehandad

414
4
13

3

votes

2 answers

Are muxes more "expensive" than other logic?

This is mostly out of curiosity. One fragment from some VHDL code that I've been working on recently resembles the following: led_q <= (pwm_d and ch_ena) when pwm_ena = '1' else ch_ena; This is a mux-style expression, of course. But it's also…

vhdl fpga xilinx synthesis

asked Dec 14 '15 at 07:10

Miral

12,637
4
53
93

3

votes

2 answers

rising_edge(clk) not synthesizable

I am learning and programming VHDL for Lattice FPGA to mimic the functionality of 74HCT245. Below is my Code. I keep getting statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition. VHDL-1242 error, entity…

vhdl synthesis

asked May 14 '15 at 15:49

am23

31
3

3

votes

2 answers

how does synthesis translate_off work?

I have a code with the following structure -- synthesis translate_off ... some sort of memory implementation/coding -- synthesis translate_on Please let me know if deleting this piece of code will affect the final output from my FPGA implementation…

vhdl implementation fpga synthesis

asked Dec 27 '14 at 04:36

Faras Dewal

33
1
4

Questions tagged [synthesis]