Illegal syntax for subtype indication VHDL200X

Question

I am trying to create a "dynamic" 2D array which I can set with generics in my entity.

I followed the example in https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-8_issue-3/articles/stream/vhdl-2008-why-it-matters_vh-v8-i3.pdf on page 32.

The declaration of my type within the package (TypeDeclarations):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package TypeDeclarations is

-- Type BusArray -----------------------------------------------------
-- Can be used by: DArray((Y - 1) downto 0)((X - 1) downto 0);      --
                                                                    --
    type TArray is array (natural range <>) of std_logic_vector;    --
                                                                    --
----------------------------------------------------------------------
end package;

my entity:

-- Libraries
library ieee;
use ieee.std_logic_1164.all;

-- Own libraries
use work.TypeDeclarations.all;

entity DynamicRegisterSet is
    generic (
        INPUT_DATAWIDTH  : integer := 1;
        OUTPUT_DATAWIDTH : integer := 8;
        N_REGISTERS      : integer := 1);
    port (
        MCLK : in std_logic := '0';
        WE   : in std_logic := '0';

        -- input data
        DATA : in std_logic_vector((INPUT_DATAWIDTH-1) downto 0) := (others => '0');
        SEL  : in integer range 0 to (INPUT_DATAWIDTH-1) := 0;

        -- in/output data (register set)
        REGISTERSET : inout TArray((N_REGISTERS-1) downto 0)((OUTPUT_DATAWIDTH-1) downto 0) := (others => (others => '0')));
end DynamicRegisterSet;

This is the first time I'm using the updated compiler (VHDL200X), I don't think I am doing this wrong but else I wouldn't get this message:

VHDL\CommonBlocks\DynamicRegisterSet\Sources\DynamicRegisterSet.vhd" Line 25: Illegal syntax for subtype indication

Anyone any suggestions? I would appreciate it very much, thanks!

lines before that are comments, it gives the error at REGISTERSET : that is line 49 — MVT, May 02 '16 at 19:06
That information should be in the question, not in a comment. Better still, compile what you post so the errors match the code. — , May 02 '16 at 19:09
@BrianDrummond I updated the error so it matches the code that I posted — MVT, May 02 '16 at 19:11
@Paebbels come again? it has the option to switch compiler does it support like half of the functions? — MVT, May 02 '16 at 19:14

score 3 · Accepted Answer · answered May 02 '16 at 19:16

3

Xilinx ISE 14.7 has no VHDL-2008 support...

They support a hand full of VHDL-2002/2008 features, but unconstrained array elements are not supported.

Vivado added VHDL-2008 support in 2016.1 and sets it as default. But as far as I can see, it's no full VHDL-2008 support.

There is a Xilinx XST synthesis user guide listing these features in the VHDL section. (Sorry I don't have the UG number on my phone.)

answered May 02 '16 at 19:16

Paebbels

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It's okay, Thanks for all the support, I'm just baffled. I thought this change was sort of official and so small that I thought It was implemented fully to keep VHDL designs compatible. I gues I was wrong :). do you know for any change that this is also the case with other FPGA manufacturers? – MVT May 02 '16 at 19:26
1

The 2008 support in Altera Quartus Prime and Lattice Diamond is better. I have no info on Symplify but I suspect it's ever better. – Paebbels May 02 '16 at 19:53
I am using lattice diamond now but I got the same error now when trying to generate a test bench :p this is not over yet – MVT May 02 '16 at 21:39
Have you enabled VHDL-2008 for Diamond? Using 2008 in synthesis (x)or testbench are two completely different things... Are you simulating with Active-HDL? – Paebbels May 02 '16 at 21:51
Double click on your active design strategy, e.g. **Area**, navigate in the *Process* tree to **Synthesize Design -> LSE**. Then scroll down to the buttom and set **VHDL 2008** to **True**. (My Diamond version is 3.7) – Paebbels May 03 '16 at 08:25
Hmm, done that for synplify pro and LSE, my version of Diamond is also 3.7 and I am using synplify pro. Still its not working for me, I also can't generate schematic symbols. Could it be that I need to generate an hierarchy first? I saw someone do this in a tutorial on creating and testing a design, this was on a older version though and I couldn't find that option. – MVT May 04 '16 at 17:10

score 0 · Answer 2 · answered Feb 21 '19 at 12:55

ISE

ISE has no VHDL-2008 support at all. Read more details on Xilinx forum or from XST guide ISE12 ISE14

Supported VHDL IEEE Standards

XST supports the following VHDL IEEE standards:

Std1076-1987

Std1076-1993

Std1076-2006

Note Std 1076-2006 is only partially implemented.

Vivado

Vivado has a set of synthetisable VHDL-2008 construct. Read more details in UG901 (Supported VHDL-2008 features chapter)

Illegal syntax for subtype indication VHDL200X

2 Answers2

ISE

Vivado