How do I get rid of sensitivity list warning when synthesizing Verilog code?

Question

I am getting the warning that:

One or more signals are missing in the sensitivity list of always block.

always@(Address)begin
  ReadData = instructMem[Address];
end

How do I get rid of this warning?

score 6 · Accepted Answer · answered Apr 22 '10 at 01:17

6

Verilog does not require signal names in the sensitivity list. Use the @* syntax to signify that the always block should be triggered whenever any of its input signals change:

always @* begin 
    ReadData = instructMem[Address]; 
end

answered Apr 22 '10 at 01:17

toolic

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if I do that then I can't synthesize it : WARNING:Xst:2319 - "InstructionMemory.v" line 20: Signal instructMem in initial block is partially initialized. The initialization will be ignored. ERROR:Xst:902 - "InstructionMemory.v" line 104: Unexpected instructMem event in always block sensitivity list. – aherlambang Apr 22 '10 at 03:26
That's a strange way to access a memory, anyways. Usually you'd end up doing a synchronous operation on the memory address and r/w ports, then take the result from its output port. That said, I'm not down with the ins and outs of using the memories of FPGAs, if that's what you're at. – Marty Apr 22 '10 at 04:36

score 1 · Answer 2 · answered Apr 22 '10 at 00:06

1

Add InstructMem to the sensitivity list.

answered Apr 22 '10 at 00:06

Brian Carlton

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score 1 · Answer 3 · edited Apr 21 '15 at 08:53

1

Declare ReadData as a wire instead of a reg and then replace your always block with an assign.

assign ReadData = instructMem[Address];

edited Apr 21 '15 at 08:53

Qiu

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answered May 01 '10 at 22:38

George

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score -1 · Answer 4 · answered May 26 '10 at 14:34

I am not sure what the declaration of instructMem looks like. Anyway, ReadData = instructMem[address] is going to result in a multiplexer with address being treated as selection logic and instructMem as data lines of the multiplexer using a typical synthesis tool. You would need to put in instructMem in the sensitivity list since whenever this changes so should ReadData.

I tried Icarus, and you anyway cannot do something like always @(instructMem or address) where instructMem has a declaration like reg [7:0] instructMem [255:0] --> implying memory.

Note: do not try to synthesize Verilog memories this way, typically you are supposed to instantiate memory IPs and connect to their ports. Vendors provide memory models for such purposes.

How do I get rid of sensitivity list warning when synthesizing Verilog code?

4 Answers4