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Questions tagged [risc]

DO NOT USE. Use the specific ISA that your question relates to instead, e.g. [arm], [mips], [riscv], [avr] or [instruction-set] for questions about instruction sets in general.

RISC systems are typically load/store in nature, whereby all instructions operate only on registers or immediate values, rather than memory. In order to work against memory the data must be loaded into a register or written from a register using memory specific instructions.

Some well known examples of RISC CPUs are ARM, MIPS, PowerPC, RISC-V and SPARC.

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Does the store word (sw) instruction in MIPS have dependencies on both the rt and rs field?

For example in a 5 stage pipeline with the following instruction set: add $t3, $t1, $t2 add $t6, $t4, $t5 sw $t3, 4($t6) //is there a dependency on $t3 and $t6? add $t6, $t6, $t3 //does the add have to wait until sw stores $t3 into the memory? I…
LordOfFlies
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Are WAW and WAR hazards unique to RISC processors?

Whenever I find something on hazard, I find it in the context of RISC processors like MIPS. Are WAW and WAR hazards unique to RISC processors? Or, CISCs can also encounter those hazards?
user366312
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Renesas M32R Processor preocedural call and returns

How do I create a procedure in an Renesas M32R ISA? how do I call it and how do I return it? There aren't many documentation on this ISA on the internet. Is it the same as Arm's procedure call?
Sabir Asmare
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Compiler: transformation of intermediate representation variables to native code

On books, articles, slides and tutorials about intermediate representation used in compilers, the Three Address Code (TAC) is a common one. My question is about the following examples of TAC t0 = a t1 = a + b a = t2 In this example, we have three…
Hadley Siqueira
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RISC access address greater than largest integer register

Let's say you are running a 32-bit RISC system. What instructions would you use to access a 64-bit memory address? In a CISC instruction set, you can simply pass the extra word using a multiword instruction. For example: 1a) JMP 1b) loAddress 1c)…
Jet Blue
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Example with MIPS, Pipelining and Branch Delay Slot

I am preparing for a test and have such example. Following code: 1: SLL $1, $1, 2 2: LW $2, 1000($1) 3: BEQL $2, $0, END 4: ADDI $3, $2, 1 5: MULT $3, $2 6: MFLO $4 END: 7: J QUIT ... QUIT: 100: NOP is executed on RISC processor (with quasi MIPS…
J. Doe
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Direct Arithmetic Operations on Small-sized Numbers in RISC Architectures

Are there any RISC architectures which allow arithmetic operations to be applied individually to bytes, half-words and other data cells, whose size is less than the size of the CPU general purpose registers? In Intel x86 (IA-32) and x86-64 (known as…
Victor
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How do direct number operands in a CPU work?

To give an example: a x86_64 CPU reading a 128 bit instruction. From what I understand, this is centainly a thing that happens in x86 processors. Otherwise it would not be possible to for instance add a 64-bit number to a 64 bit register (the opcode…
RabbitBones22
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Assembly language st and ld

I have converted a c program into an assembly program and am trying to simplify the code: .global Func1 Func1: save %sp, -112, %sp !st %i0, [%fp+68] !st %i1, [%fp+72] !ld [%fp+68], %o0 !ld [%fp+72], %o1 call Func2, 0 nop mov %o0, %g1 mov %g1,…
Dillon Burton
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how to implement delayslot in superscalar processors?

Back in early days, processor's pipeline was simple and branch prediction was not as accurate as now.So delay slot----statically schedule instructions by compilers,seemly was an efficient choice.But nowadays, with technology like superscalar,…
zyh_idler
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Which criteria is having lower and higher values for CISC and RISC?

Considering relative comparison of the features/properties of CISC and RISC Machines, it is needed to fill the following table (need to write only High/Low) Feature/Property CISC RISC Instruction Count in Program Low …
Tutor GRRR
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How many bits do instruction sets have in ARM?

When working with ARM, we commonly understand that the data width residing on an address is 8 bits (I hope this assumption is correct). How does the program counter increment? Does the program counter increment by 4 every time? Inferring that the…
CJC
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YASMIN CPU simulator instruction set, RISC-based but what does #h mean?

I'm working through a set of problems related to the YASMIN CPU/OS simulator with a RISC-like instruction set. (Editor's note, possibly this one or another version of it). I just cant seem to find the answer to the following: Add the following…
Aurora
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Instructions with Long (32 and 64 bit) immediate operands in RISC processors

Are operations with large immediate numbers possible in RISC processors, when the size of the immediate operand does not allow to place it in the 32-bit instruction word (standard for RISC architectures). Say we want to store a 32-bit or 64-bit…
JSpruce
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How RISC reducing cycles while having many instructions?

I quote from this site: cs.standford.edu The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the…
Citra Dewi
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