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I quote from this site: cs.standford.edu

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.

It said RISC reducing the cycles per instruction at the cost many instructions will be used, how it possible?

AFAIK, one cycle of CPU is defined as:

  • fetch (instruction)
  • decode (instruction)
  • execute

So can I conclude more instructions mean more cycles?

Citra Dewi
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1 Answers1

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No, one cycle is one period of the clock, not of executing a whole instruction. (e.g. for a 100MHz CPU, one clock cycle is 1/100MHz, or 10 nanoseconds.)

RISC was designed to make pipelining easier (and thus possible in the early 1980s) so those stages of execution could overlap in separate instructions. See Modern Microprocessors A 90-Minute Guide! and https://en.wikipedia.org/wiki/Classic_RISC_pipeline

So can I conclude more instructions mean more cycles?

No. Basically unrelated.

The maximum complexity of any single instruction is what matters, not how many different opcodes the CPU supports. Look at modern AArch64 and PowerPC for example: many different instructions (including SIMD), but each one has an upper limit on how much it can do, so they generally don't need microcode. A limit on the number of register reads and writes per instruction, any computation is something you can build into a pipelined ALU, and memory is only accessed by load/store instructions that don't also do math. (The last point is what makes a machine a "load store" machine.)

The part of the RISC idea that's still truly useful is Reduced Instruction-Set Complexity. e.g. not things like x86's rep stosb (arbitrary-length memset). And also avoiding stuff like x86's partial-flag updates on instructions like rol that leave some FLAGS unmodified but write others. That can be worked around by modern high-performance CPUs, but is still a penalty.

And most obviously, memory-destination instructions like add [rdi], eax that internally have to load / add / store are very non-RISC.

Peter Cordes
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  • From your example, 1 cycle is 10 nanosecond. Does it mean 10 nanosecond is time needed for CPU to execute 1 instruction? – Citra Dewi Jul 23 '22 at 19:26
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    @CitraDewi: No. Go read https://www.lighterra.com/papers/modernmicroprocessors/ re: average cycles per instruction, and pipelining. A typical scalar RISC pipeline (like MIPS R2000) can *start* a new instruction every cycle, but that doesn't mean the whole process of executing a single instruction happens in one cycle. Modern in-order pipelines CPUs can often start 3 or more instructions per cycle, like ARM Cortex-A53. And out-of-order exec allows it to pick any 4 to 6 independent instructions to start per cycle. – Peter Cordes Jul 23 '22 at 19:28
  • What is CPI value in figure 6 about superpipelining in your link you refferenced? – Citra Dewi Jul 23 '22 at 19:59
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    @CitraDewi: From the text right before it: *but the processor will still be completing **1 instruction per cycle (throughput)**, and there will be more cycles per second, so the processor will complete more instructions per second (actual performance)...* They're just talking about longer pipelines, not wider pipelines that could give you an average cycles-per-instruction below 1 like modern CPUs. – Peter Cordes Jul 23 '22 at 20:01