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Questions tagged [risc]

DO NOT USE. Use the specific ISA that your question relates to instead, e.g. [arm], [mips], [riscv], [avr] or [instruction-set] for questions about instruction sets in general.

RISC systems are typically load/store in nature, whereby all instructions operate only on registers or immediate values, rather than memory. In order to work against memory the data must be loaded into a register or written from a register using memory specific instructions.

Some well known examples of RISC CPUs are ARM, MIPS, PowerPC, RISC-V and SPARC.

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SimpleRisc Program to find in how many ways can a 32 bit number be rotated to give the same number

Given to write a program to find in how many ways can a 32 bit number be rotated to give the same number. mov R0, 1431655765 mov R6,R0 mov R5,31 mov R4,0 .loop : cmp R5,0 beq .exit lsl R2,R0,31 lsr…
Sahay
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Translating uppercase conversion function from C to MIPS

How can I convert this code to MIPS? I don't understand how each character in an input character pointer can be converted in MIPS. void toUpper(char *s) { int n = strlen(s); int i; for (i = 0; i < n; i++) { s[i] &= 0xdf; } }
zzzOp
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Mips Looping If-Else Statements

I am trying to create a mips program that will go through 3 if/if-else statements and loop them 10 times. I am having difficulty understanding how to make a label to loop other labels or if there is another method. My code is as follows: .data …
simplest
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Where to find description for @hi and @lo "instructions" of OR1K assembly

I'm learning OR1K assembly for a project I'm working on. clang and LLVM are used to provide front end and the back end for the compiler. I found this link and it is almost everything I need, however assembly I'm looking at has @hi and @lo symbols in…
flashburn
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Setup RISC-V toolchain with specific instruction set

I'm developing a processor using a form of the RISC-V ISA and i'm currently trying to setup the toolchain. My current processor design uses the RV32I base instruction set and i want to compile for this ISA. However the default configuration of the…
Peter Verbrugge
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sparc assembly - add and addcc

I have just read some old courses on SPARC Assembly and I don't remember the difference between "add" and "addcc" instructions (like also sub and subcc). Could you explain to me this difference ? Thanks
user1773603
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Are IA64 and SPARC chips RISC or CISC architecture?

I have a very basic questions about these architectures are these architecture RISC-based or CISC-based? pipeline stages in both and instruction set format for both Please help me
vicky
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How to perform right shift on RISC

I'd like to know how I can perform a right shift on a Reduced Instruction Set Computer that does not offer this operation on it's own. A left shift can be simply done by adding a register to itself but how about a right shift? The RISC offers…
xuma202
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Is there a flag register in the Power ISA?

Is there a flag register in the Power ISA, similar to EFLAGS in the x86 machines? It could have some other name, for example it could be called "Status Register" or something of that kind, but its purpose would be saving some general attributes of…
JSpruce
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Assembly language files. Whats the differnce?

What are some good courses online to learn assembly code. I have seen a few courses but they all teach using .asm files. I am trying to learn assembly where files have an extension of .s Also what are main differences between these 2 types of…
Abdullah Meda
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Do RISC processors not have backward compatibility?

I'm reading a textbook which says: RISC processors have done very well in the market for embedded processors, controlling such systems as cellular telephones, automobile brakes, and Internet appliances. In these applications, saving on cost and…
user11224591
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Which program will be bigger in size - RISC or CISC?

Let's say I have a hello world program, which print 'Hello World'. Now, I have compiled this program for CISC Processor and next I have compiled for RISC processor. My question is which will have bigger code size and why?
Prawn Hongs
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Verilog Icarus giving undefined values

I'm working on a project in which I'm designing a simple RISC machine in Icarus Verilog 0.9.7. This code is modular and I'm going to put together the several components in the end, but I've run into an issue while working on the Memory Controller.…
Stan
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what are the advantages of implementing register in microcontroller architectures i.e. load store architecture

Major difference in RISC and CISC is that in RISC we must need to use registers to do any arithmetic or logic operation. But in case of CISC we can do such operation directly with memory locations. So what is the advantage of implementing register…
shreyas_patel21
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RISC Emulator/Compiler

Question: is there a (preferably online or Linux-operational) RISC compiler, with an interface to display the register contents and such without requiring hardware? (I suppose a simple emulator of sorts is what I'm looking for.) Background: I've…
sami
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