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Questions tagged [risc]

DO NOT USE. Use the specific ISA that your question relates to instead, e.g. [arm], [mips], [riscv], [avr] or [instruction-set] for questions about instruction sets in general.

RISC systems are typically load/store in nature, whereby all instructions operate only on registers or immediate values, rather than memory. In order to work against memory the data must be loaded into a register or written from a register using memory specific instructions.

Some well known examples of RISC CPUs are ARM, MIPS, PowerPC, RISC-V and SPARC.

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I cannot find a solution to muliply unsigned integers

I tried to make a program which read 64 bit integer into two registers on RARS. Then, when multiplying 32 bit unsigned integers by 10, I wrote mulhu s3, s3, s2 #s2 is 10 , but s3 doesn't change form 0. Then when I wrote mul s3, s3, s2 it worked,…
Sotaro Suzuki
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Different structures in out of order processors

I am studying the out of order processors, so in different types of out of order processors, there are different structures like ARF(architectural register file), PRF(physical register file), ROB(reorder buffer) and FSB(Finished store buffer). Which…
Neeraj Singh
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What is the value x12 at the end of the execution of this instruction in RISC-V? (WITHOUT RARS)

I need to know what is the value of x12 knowing that x13=10 ( without using rars ) these are the code lines loop: blt x13,x0,EXIT addi x13,x13, -1 addi x12,x12,2 jal x0, loop exit:
exiturnor
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CISC mul vs RISC mul instruction

I'm trying to understand the difference between CISC and RISC architecture. I read this to understand the difference between CISC and RISC arhictecture but I'm confused. There is a sentence in the article like that MULT is what is known as a…
beginner_dv
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pow(float x, float y) in RISC Assembly

I am writing a compiler for a variation of Fortran to MIPS as an assignment for the University. In that language, power operator is built-in, exactly like Python where you can say a ** b and it's done. So, in some point I have to write assembly for…
Constantinos Petrakis
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How are POSIX and RISC/CISC related

I understand that POSIX is a set of standards for a system interface. I understand the RISC and CISC define a set of standard commands for a CPU. To me, that sounds like the same thing. How are POSIX and RISC different/related? Thanks in advance!
J Seabolt
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Why are CISC instructions considered to be easier/faster to compile than RISC instructions?

Many websites and textbooks state that CISC instructions are easier or faster to compile than RISC instructions. I've been having a hard time finding a definite, comprehensive reason for this, one textbook states that it's because CISC instructions…
Pzet
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When does the pipeline take 2 decode stages when there is a RAW dependency in 2 successive instructions

Consider a RISC pipeline having 5 stages, Find how many cycles are required for the instruction given below, assume operand forwarding, branch prediction is used in which the branch is not taken, ACS is the branch instruction and the five stages are…
Olivia Pearls
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The memory footprint of a program for a RISC processor

How can I test the memory footprints programs written for a RISC and a CISC processor? Which one would require more memory and why?
user366312
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How to implement CISC Pipelined CPU right?

I'm working on the project for my graduation in college. I already did one pipelined CPU and simulated it in Logisim program for one of my courses, but now I need to flash CPU to my FPGA and write game for this CPU also. So I thought to improve my…
Stanislav Ryzhkov
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How to calculate average CPI for a pipelined processor?

For a question on a practice exam, it asks: Consider a program consisting of 100 ld instructions in which each instruction is dependent on the instruction immediately preceding it, e.g., ld x2,0(x1) ld x3,0(x2) ld x4,0(x3) What would the average…
user4802956
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MIPS wired logic DPU

I am a student and i have an exercise on MIPS and i need some guidance! Below is the exercise: Consider the Data Processing Unit of MIPS architecture wired logic for a command cycle for single and multiple machine cycles. Describe the full flow of…
Δημητρης Ρόκκος
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Can I implement Branch target buffer in two stage pipelined RISC architecture?

I am trying to implement the BTB in low-level microcontroller such as PIC16. I don't know is it feasible or not. So wanted your suggestion. Thanks.
Pratik Katwate
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Adding two numbers in assembly language

What I am attempting is to compare 2 numbers in assembly language and display the largest of the two numbers, as shown in the pseudo code below. I am using this website here to do this http://www.peterhigginson.co.uk/RISC/ Here is what I am came up…
Lewis Watkins
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why an explicit single-cycle datapath is not needed?

Why does the PC not need an explicit write signal in a single-cycle datapath? Why is an explicit write control signal needed in a multicycle datapath? Thank you
user3142443
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