I want to type conversion in Quartus2 Verilog.......
integer to reg
ex)
integer a = 10;
reg[3:0] b;
$cast(b,a);
but $cast is not supported synthesis..
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There is no need to explicitly cast between integral types; Verilog is loosely typed and defines implicit casts between many different types. You can just write:
b = a;
Explicit casts is a SystemVerilog feature having two different forms: static and dynamic.
You use a static cast to a built-in or used defined type:
typedef reg [3:0] uint4_t;
b = uint4_t'(a);
And that would be acceptable for synthesis.
The dynamic $cast operator is targeted for class variable assignments with inheritance. It would not expect synthesis tools to support this.
dave_59
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In my quartus, tpyedef is not available..... Is there any other way? – chundeuk Jun 08 '21 at 17:47
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You can just write `b= a;` there is no need for a cast. In any case `typedfef` should be available if you turn on SystemVerilog. – dave_59 Jun 08 '21 at 17:49
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thank you very much. but typedef really does not work. so solved it b=a – chundeuk Jun 08 '21 at 18:13