Quartus RTL viewer parameter is not synchronous with VHDL code. Error (10344) VHDL

Question

I'm doing my project by referring to "https://github.com/eigenpi/Face-Detection-on-FPGA"'s project. I planning to change the OV7670 camera to Terasic-D5M camera. I try to change the input parameter bits from 8 bits to 12 bits but it shows error 10344. I changed both the parameter in the top-level entity and the connected function input. I checked with the Quartus RTL viewer and it shows that the pin name is changed but the parameter maintained as the old value (8 bits). Anyone know the problem or any pre-setting that cause I failed to change the parameter? Thank you.

Answer 1

Error 10344 is due to a bit range mismatch, which you have appeared to fix in that you can compile it and view the new RTL.

However, if you don't make use of the extra 4 bits, they will be optimised out during compilation/synthesis.

To change the camera data from 8 bits to 12 bits, you need to change the bit range of the following signals, and make use of all the bits as per the tech spec of the new camera:

• ov7670_data
• d
• latched_d
• d_latch
• dout

Also beware of ov7670_pwdn and ov7670_reset and other camera control signals that may be different for the new camera.

As you have discovered, trying to change the existing camera controller to control the new camera is difficult if not impossible.

So it would be best to replace the existing controller with the D5M controller from the Terasic demo.

top.vhd

Line 78:

    ov7670_data : in  STD_LOGIC_VECTOR(7 downto 0);

Line 522:

  Inst_ov7670_capture: ov7670_capture PORT MAP(
    pclk  => ov7670_pclk,
    capture => take_snapshot,
    vsync => ov7670_vsync,
    href  => ov7670_href,
    d     => ov7670_data,
    addr  => image_wraddress_from_ov7670_capture,
    dout  => image_wrdata_from_ov7670_capture,
    we    => image_wren_from_ov7670_capture,
    busy  => ov7670_capture_busy
  );

ov7670_capture.vhd

entity ov7670_capture is
  Port ( pclk  : in   STD_LOGIC;
    capture : in STD_LOGIC; -- recieves signal from a button to begin a single frame capture
    vsync : in   STD_LOGIC;
    href  : in   STD_LOGIC;
    d     : in   STD_LOGIC_VECTOR (7 downto 0);
    addr  : out  STD_LOGIC_VECTOR (16 downto 0);
    dout  : out  STD_LOGIC_VECTOR (11 downto 0);
    we    : out  STD_LOGIC;
    busy  : out  STD_LOGIC
  );
end ov7670_capture;

Line 33:

  signal d_latch      : std_logic_vector(15 downto 0) := (others => '0');

Line 41:

  signal latched_d     : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');

Line 48:

  dout <= d_latch(15 downto 12) & d_latch(10 downto 7) & d_latch(4 downto 1); 

Line 77:

      -- capturing the data from the camera, 12-bit RGB
      if latched_href = '1' then
        d_latch <= d_latch( 7 downto 0) & latched_d;
      end if;

Line 110:

      latched_d     <= d;

Compiling the Original

Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "vga_sync_N" is stuck at VCC
    Warning (13410): Pin "ov7670_pwdn" is stuck at GND
    Warning (13410): Pin "ov7670_reset" is stuck at VCC