Quartus Prime (SystemVerilog) - Why does a testbench have to be synthesizable to simulate using ModelSim?

Question

I am trying to verify the functionality of a 32-bit adder module using a testbench. I want to test the adder using random inputs and the testbench code is as follows:

`timescale 1ns/1ps

module adder_tb();

    parameter N = 32;
    logic [N-1:0] a, b, s;
    logic cin = 0;
    logic cout;
    
    cascaded_32_adder adder32 (.*);
    
    initial begin
        repeat(200) begin 
            #10
            a = $urandom;
            b = $urandom;
            assert ({cout,s} == a + b + cin) else $error("%d+%d+%d != {%d,%d}", a, b, cin, cout, s);
        end
    end
    
    
endmodule

I have tried running similar testbenches in EDA Playground before and had no issues. However, in Quartus (I am using the Quartus Prime 20.1 Lite edition), when I do Analysis and Synthesis (not full compilation) with this testbench as the top level entity, it gives the following error:

Error (10174): Verilog HDL Unsupported Feature error at adder_tb.sv(15): system function "$urandom" is not supported for synthesis

If I try to run the RTL simulation using ModelSim afterwards, it says that "Analysis and Synthesis should be completed successfully before starting RTL NativeLink Simulation".

I understand that a function like $urandom is not synthesizable, but why is this a requirement for running a ModelSim simulation? I have not changed any project settings from the defaults in Quartus.

If there is no workaround for this, please let me know if there is another easy way of verifying a module with random inputs in Quartus.