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Questions tagged [modelsim]

ModelSim is a popular simulator and debugging environment for VHDL, Verilog and SystemC. It is used in electronic design automation for development and verification of electronic (mainly digital) modules and systems for implementation on field-programmable gate arrays or integrated circuits.

ModelSim is a product by Mentor Graphics to simulate systems written in one of the hardware description languages (HDLs) VHDL or Verilog or the system-level modeling language SystemC.

Depending on the license, ModelSim offers all or a subset of the following features:

  • Source code editor
  • Compiler
  • Simulator
  • Waveform viewer
  • Interactive debugging such as breakpoints, stepping etc.
  • Signal tracing (dataflow) analysis
  • Code coverage analysis
  • Functional coverage analysis
  • Project file management

ModelSim integrates these features in a single configurable GUI, however, it can also be scripted via the Tcl language and controlled through command-line parameters which allows for automation of simulation and verification tasks.

756 questions
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How to add all Modelsim waveform?

I'm currently working with a big project with many module and sub-module inside. Is it possible (GUI or tcl scripts) to add all wave and group it in tree like module-tree? For example: module A include module b0, b1, b2, b3,..., b10. I want to add…
Khanh N. Dang
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Is it possible to write verification procedures on simulations in ModelSim?

I am using ModelSim in order to design and simulate CPU architectures. For those like me who know about this, you are also probably aware that it is really difficult to verify simulation data when trying to handle all those signals in front of…
Andry
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ModelSim PE Student Edition 10.1c (STD_LOGIC error)

I am trying to use STD_LOGIC in my VHDL code. It will not compile because the STD_LOGIC I am trying to use in the port(.....) section is not working. I know the problem is because I did not import the IEEE library. I tried to import it but I was not…
TerNovi
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Creating an array in Verilog using ModelSim

I am trying to declare a 1MB memory model using an array in Verilog in ModelSim using the code below. I also need to have the address 0x80020000 within the address space. parameter MEM_START = 32'h7FFA_0000; parameter MEM_END = 32'h800A_0000; reg…
terfex
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How to Simulate PCIe Design Using BFMs? Intel PCIe_DDR Design

I am trying to simulate the reference design (PCIe_DDR4) on Terasic DE5a-Net DDR4 edition board. I want to simulate this and confirm meaningful DDR4 read/writes in ModelSim. Referring to Intel Documentation :…
baggins6000
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Quartus Prime (SystemVerilog) - Why does a testbench have to be synthesizable to simulate using ModelSim?

I am trying to verify the functionality of a 32-bit adder module using a testbench. I want to test the adder using random inputs and the testbench code is as follows: `timescale 1ns/1ps module adder_tb(); parameter N = 32; logic [N-1:0] a,…
anuki16
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How to show enumeration value of variable, rather than the bit vector value in ModelSim

I'm currently working on a final project for my Verilog course, which involves building a processor. As part of this project, I've created a state machine, and I'm trying to visualize the names of the states in the waveform window. However, it seems…
Yonatan Shkolsky
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How to restart ModelSim co-simulation from MATLAB testbench?

I am working on an iterative co-simulation process. What I need to do is to either restart the ModelSim simulation from the main hdl program or from MATLAB script/testbench. Currently, I am restarting the simulation manually (Simulate-->Restart),…
Bilal MEJMAA
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ModelSim Install in Ubuntu 22.04

I am using Ubuntu 22.04 LTS as my OS system. I need to install modelSim for participating Verilog or HDL . But I am failed to do it. How to Install ModelSim in Ubuntu 22.04 ? Is there any terminal command? I downloaded modelSim Version from "Intel…
Shahrear Al Sakib
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Modelsim 2021.4 (Windows): How to exclude files from code coverage report

I am trying to exclude certain vhdl files from my code coverage report, but I can't get it to work. My report always shows all available files. My workflow is as follows: in Modelsim I compile the files manually (in the GUI) with the Code Coverage…
Hirsch
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why does my Verilog adder-subtractor fail the addition here with 1 more than correct answer?

I wrote a 4-bit full-adder-subtractor, and my code managed to operate subtraction but failed operating addition with 1 more than the correct answer: 0101+0101=1011. Help! Here's the full-adder-subtractor code: module Add_sub(x,y,co,u,en); input…
JarvisLYu1
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VHDL problem with a counter and its simulation

I did a counter like i normally do on VHDL (Modelsim) and when i simulate my code with my testbench all the counters do not work at all. They stay at 0. Here is the code for the counter: process(CLK) begin if (CLK'event AND CLK='1') then if…
Àlex López Nadal
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Nonresolved signal has multiple sources whereas i drive it once (VHDL)

i have a problem with my VHDL code. i am getting an error "Nonresolved signal 'temp' has multiple sources." . I tried different things : first, i had this : adc_integer_expected <= integer(volt_db(index)(lane) / (ADC_VOLT_MAX/4096.0)); But it…
mugen54
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Counting instances of modules in SystemVerilog

I am attempting to design a simple CPU and I ma using SystemVerilog to design and ModelSim to simulate the design. I am trying to set up some code to count the number of instances of a specific module. I am currently using static variables to try to…
finlay morrison
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How I can use swap 32 bits in Verilog? example: (Bit 0 is copied to position 31 Bit 31 is copied to position 0)

How I can use swap 32 bits in Verilog? example: (Bit 0 is copied to position 31 Bit 31 is copied to position 0) p[0] <= p[31]; p[31] <= p[0];
Walaa Fadaleh
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