I am trying to simulate the reference design (PCIe_DDR4) on Terasic DE5a-Net DDR4 edition board. I want to simulate this and confirm meaningful DDR4 read/writes in ModelSim.
Referring to Intel Documentation : https://www.intel.com/content/www/us/en/docs/programmable/683162/23-1-2-7-0/simulating-external-memory-interface.html
It suggests to do the following: Section 2.6
To my understanding this sources the generated msim_setup.tcl which loads design and device files, etc. But is not responsible for driving the design. I do get objects in Windows but they do nothing as it it not being provided any stimulus.
1. Is the procedure incomplete or am I missing something?
There should be a testbench which would drive the simulation. Since it is PCIe Hard IP, I came across recommendations for using Bus Functional Modules(BFMs) for simulation testing. I do not have experience in it or systemverilog.
2. Is there an Intel example where BFMs are being used for simulation?
Many system generated BFMs are making it difficult for me to design my own BFM tesbench.
The Reference Design Schematic
I found this thread to be useful in getting some idea: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Avalon-BFM-Test-Program/m-p/111682
But I am struggling to get my testbench properly setup. Namely:
- The model instantiantion: I am using the instantiation template from the file created inside sim directory by Platform Designer. This file is in the same level as the mentor directory. It is named ep_g3x8_avmm256_integrated_tb.v I manually searched and found this. I could not find any recommendation on TB instantiation.
- Correct BFM: The setup script has several BFMs for DDR itself. It is my guessing one of them to be the right BFM, I do not know for certain.
Part of this is also because of my inexperience in systemverilog.
Any help is appreciated. I can happily provide any more information.
