0

I am trying to use STD_LOGIC in my VHDL code. It will not compile because the STD_LOGIC I am trying to use in the port(.....) section is not working. I know the problem is because I did not import the IEEE library. I tried to import it but I was not successful.

How to import the IEEE library properly to a VHDL program in ModelSim?

Qiu
  • 5,651
  • 10
  • 49
  • 56
TerNovi
  • 390
  • 5
  • 16

1 Answers1

0

To import the package that defines the std_logic type to a VHDL design, add the following two lines to the top of your VHDL file:

library ieee;
use ieee.std_logic_1164.all;
pc3e
  • 1,299
  • 11
  • 18