Verilog-A & Verilog ; Are they the same?

Question

• Is Verilog-A the same as Verilog ?
• Is there a testing compiler for Verilog-A?

Because when I just paste some sources code of Verilog-A on ModelSim, there are always some errors that can't be removed. Can ModelSim run Verilog-A?

Answer 1

Verilog-A and Verilog are related but very different.

Verilog was standardized first and is usually for describing the behaviour of digital circuits and testbenches. Verilog is event driven. Analog behaviour can be simulated in testbenches, but modelling of analog behavior can be difficult.

Verilog-a was standardized later, and was based on the syntax of verilog. It is intended for the modelling of analog circuits. The two languages are not compatible, both having constructs that the other does not support. Verilog-a can simulate continuous time behaviour, like spice/spectre simulators. It does not model digital behaviour very well. Modelsim, or other 'Verilog simulators' do not support Verilog-a - it is mostly supported by spice simulators.

Verilog-AMS is an evolution of Verilog-a, which allows both analog and digital constructs to co-exist in the same file/block. However, it again only supports a subset of modern verilog. It is not supported by the standard Verilog simulators - again support is more on the analog/spice/spectre simulators.

Answer 2

1. Verilog-A HDL is derived from the IEEE 1364 Verilog HDL specification, but they aren't the same.
2. I think that this question can help you find what you are looking for.

Answer 3

Verilog is a deprecated standard for digital hardware description. Formally that last version was IEEE 1364-2005. It has been superseded by SystemVerilog (IEEE 1800-2017). Though deprecated, many tools still support it.

Verilog-A is an analog extension. Unlike its digital counterpart, the language is only for verification (simulation), it cannot be synthesized. It was standardized by the "Open Verilog International" trade association. Later the standard was incorporated as a subset of Verilog-AMS (analog and mixed signal extensions to Verilog).

If you want to simulate Verilog-A you will need a suitable simulator. This could be a mixed signal simulator (VCS AMS, Questa ADMS or Allegro AMS for instance). Alternatively most commercial SPICE simulators support Verilog-A.

Answer 4

Verilog-A is not the same as Verilog.

Verilog is used to describe digital circuits whereas Verilog-A is used to model the behavior of analog circuits.

Verilog runs on event-driven simulators whereas Verilog-A requires a continuous time, spice-like simulator.

Event-driven simulators are orders of magnitude faster than continuous time simulators because, as opposed to the latter, event-driven simulators don't require the computation of voltages and currents for each and every circuit node. Signals are abstracted as 1 and 0s and net evaluation is triggered only when the driver is updated.

I am not aware of free simulators supporting Verilog-A and/or Verilog-AMS (the mixed-signal flavor or Verilog)

On the other hand, verilator is a great choice for (digital) verilog simulation. It also supports some constructs of verilog-ams such as wreal.