Is a <= a + 1 a good practice in VHDL?

Question

If I write the statement to assign a to be a+1 in a VHDL process, is it a good practice?

I am confused about this because the simulator works fine, but when I try to implement it in FPGA the synthesis tool complains about creating latches.

What does this mean?

Latches are implied if it sometimes holds the value, but you have not specified it in a clocked block. — Morgan, Mar 12 '13 at 22:19

score 7 · Accepted Answer · answered Mar 13 '13 at 06:40

you should do such a statement only in a clocked process. if you want to have it synthesised, an additional initialisation (reset) is suggested. might look as follows:

process(clk, reset)
begin
   if reset='1' then
      a <= 0;
   elsif rising_edge(clk) then
      a <= a + 1;
   end if;
end process;

score 5 · Answer 2 · answered Mar 12 '13 at 22:38

5

In a clocked process, this is fine. Anywhere else, probably not.

answered Mar 12 '13 at 22:38

Martin Thompson · Answer 3 · 2013-04-18T11:07:37.797

Do it in a clocked process, that's fine. What it means is "the next value of a should be the current value of a +1"

If you do it as a continuous assignment (outside of any process), what you are saying is "a is always getting a+1 assigned to it" which is a self-referential loop!

If you include a in the sensitivity list of an enabled process, you get the same effect

process (en, a)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

(You can use this form to create transparent latches:

process (en, insig)
begin
   if en = '1' then 
      a <= insig;
   end if;
end process;

)

If you do it in a non-clocked process, which is not sensitive to a:

process (en)
begin
   if en = '1' then 
      a <= a + 1;
   end if;
end process;

You will create a positive-edge-triggered latch, as a needs to keep its value between changes of en. Effectively, en becomes a clock to a d-type flipflop.

Actually, in your last example Altera's synthesis tool will implement `a` as a register clocked by `en`. (Which is arguably correct, no need to check for en'event since there's no asynchronous reset.) Still this is probably not a good idea! — pc3e, Apr 18 '13 at 08:29

Is a <= a + 1 a good practice in VHDL?

3 Answers3