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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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Problem with reset Johson Counter Verilog

I need to build the testbench and the design for a n-bit Johnson Counter, but I'm having problem with the reset of the circuit. The initial state should be 000, but I'm getting xxx. This happens for all n values. In this case, I'm testing with n =…
Carlos Eduardo Fontaneli
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Why does iverilog generate a syntax error for always_ff?

I recently started System Verilog and I'm a bit dumbfounded by a syntax error. Given the following module: test.sv : module test( input logic clk, output logic out ); always_ff @(posedge clk) begin out = 1'b1; end endmodule When…
Moritz Mossböck
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Icarus verilog: reg show; cannot be driven by primitives or continuous assignment

I am trying to port some Verilog source code to SystemVerilog. This question is specific to Icarus Verilog (tested with 10.3 and 11 providing the same result), since I did not get any errors with tools (e.g. Yosys 0.9.0, Cadence Xcelium 19.09). The…
meisterluk
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How can I make each module instance read from a unique file?

In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; …
fgjt
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8 bit sequential multiplier using add and shift

I'm designing an 8-bit signed sequential multiplier using Verilog. The inputs are clk (clock), rst (reset), a (8 bit multiplier), b (8 bit multiplicand), and the outputs are p (product) and rdy (ready signal, indicating multiplication is over). For…
SacredMechanic
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How can i list all hierarcheis of modules/submodules in verilog/system verilog?

I want to view a list of all modules/sub-modules/instances in verilog/system-verilog compilation; is that possible? I know i can do a %m in $display and it will show the hierarchy of that particular instance. I want to get a similar list but for…
justrajdeep
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Verilog testbench outputs are x and z on a 16-bit carry adder

I've been trying to reproduce a 16-bit Adder, but I can't seem to get any results on my testbench. Any leads? module adder(a,b,c,s,cout); input a,b,c; output s,cout; xor #1 g1(w1,a,b), g2(s,w1,c); and #1 g3(w2,c,b), g4(w3,c,a), g5(w4,a,b); or…
BlueBook
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Constant padding in Verilog

Here is the example behavioral Verilog code in question module constant; reg [7:0] foo; initial begin foo = 1'bz; $display("%H", foo); end endmodule Icarus Verilog gave me $ iverilog -o constant constant.v $…
nalzok
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How to know what control signals a MIPS instruction generates?

I'm creating a simulation in Verilog. I have a memory module, loaded with MIPS instructions like so... 20082000 200d2030 8dad0000 240a0001 ad0a0000 .. .. .. the memory module outputs the instruction to the input of a "Control" module, this module…
Rijad Hadzic
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myhdl cosimulation test fail

I am trying to download myhld on ubuntu and also install the cosimulation. myhdl was installed fine but when following the cosimulation installation i am unable to properly run the test case provided within the download package. an error is coming…
gauravr
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4 bit adder-subtractor in verilog

I am writing verilog code for 4 bit adder subtractor. I am using structural design. At first I have written verilog code for 1 bit full adder. Then I am using that to write code for 4 bit adder subtractor . module fadder (A, B, Cin, Sum, Cout); …
Subhadip
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code for clock generation in structural verilog

I was trying to teach myself verilog programming from "The Verilog HDL" book by Thomas Moorby. In one of the exercises, they asked to generate a clock using structural verilog only (except for the $monitor part of course). I tried the…
aditya
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Verilog program not getting desired output on 4x1 mux

I have this program I am suppose to make for this diagram 4x2 decoder diagram: I keep trying to change the initial values of the output array from 0 to 1 and 1 to 0 by just negating them but I still never get the desired result. 4x1 mux module…
T.H.
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Verilog: primitives or continuous assignment

I am running this code module neuron_xor(x0, x1, y4); input signed [4:0] x0, x1; reg signed [4:0] w02, w03, w12, w13, w24, w34; reg signed [4:0] th2, th3, th4; wire signed [4:0] y2, y3; output signed [4:0] y4; neuron n2(x0,…
Dániel Tóth
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iverilog testbench error: input is declared as wire, but it isn't

I am very new to iverilog and am creating a counter to reduce a 100Mhz clock frequency to something easier to work with, as part of a larger project. I found some code that does that and so I tried to write a testbench for it. Here is the code I…
Ross Satchell
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