I can't compile a .sv file (SystemVerilog)

Question

I'm learning SystemVerilog for the university. I installed the extensions in Visual Studio Code for syntax highlighting: SystemVerilog, Verilog-HDL/SystemVerilog/Bluespec SystemVerilog (Names of extensions). I installed the compiler Icarus Verilog and inserted the address in the environment variables (PATH).

So I copied this code:

module adder
(s, b, c_in, sum, c_out);
    input logic [7:0] a;
    input logic [7:0] b;
    input logic c_in;
    output logic [7:0] sum;
    output logic c_out;

    logic [8:0] result;

    assign result = a + b + c_in;
    assign sum = result [7:0];
    assign c_out = result[8];

endmodule: adder

And tried to run it, but it gave me this error:

Module end labels require SystemVerilog.

I even tried to compile from the cmd with the same result.

A thing that I noticed is that when I do the same thing with a .v file (Verilog), it works.

toolic · Accepted Answer · 2021-01-30T16:40:21.340

I get a compile error in your port list. Change:

(s, b, c_in, sum, c_out);

to:

(a, b, c_in, sum, c_out);

You didn't declare a in the list, and you use a in the code. s is not in the code.

After that change, your code is legal SystemVerilog syntax, and it compiles without errors on multiple simulators on edaplayground.

I did get different compile errors from yours with Icarus Verilog 0.10.0 on edaplayground. Perhaps you are compiling with a different version. Keep in mind that iverilog does not support all SV features yet.

If the module label is still causing problems for you, you can simply remove it because it is optional. Change:

endmodule: adder

to:

endmodule

Regarding the file extensions (.v and .sv), some compilers will automatically enable SV features when you use .sv; perhaps some even require .sv. Since your code uses an SV keyword (logic), you must have SV features enabled to compile.

Here is a version of your code that does not rely on SV features:

module adder
(a, b, c_in, sum, c_out);
    input [7:0] a;
    input [7:0] b;
    input c_in;
    output [7:0] sum;
    output c_out;

    wire [8:0] result;

    assign result = a + b + c_in;
    assign sum = result [7:0];
    assign c_out = result[8];
endmodule

Using logic in the port declarations is optional, and you can declare result as a wire.

I can't compile a .sv file (SystemVerilog)

1 Answers1