Problems running a test in Verilog

Question

I was trying to run a testbench on Verilog, but I keep running into some problems. I added the errors at the end for y'all to see them.

Here is the module:

module combinational_logic(
    A, 
    B,  
    C,
    D,
    AnotCnotD,
    BCDnot,
    ACnotDnot,
    F,
    );

    input A;
    input B;
    input C;
    input D;
    


    output F;
    output AnotCnotD;
    output BCDnot;
    output ACnotDnot;
    

     
    assign AnotCnotD = ~A&~C&D;
    assign BCDnot = B&C&~D;
    assign ACnotDnot = A&~C&~D;
    assign F = AnotCnotD|CDnot|ACnotDnot;
     
    
    
    
endmodule

and here is the test:

`include "project4.v"
module tb_combLogic;


    
    reg A;
    reg B;
    reg C;
    reg D;
    reg F;

    
    wire AnotCnotD;
    wire BCDnot;
    wire ACnotDnot;

    
    combinational_logic uut (
        .A(A), 
        .B(B), 
        .C(C),
        .D(D),
        .AnotCnotD(AnotCnotD),
        .BCDnot(BCDnot),
        .ACnotDnot(ACnotDnot)
    );

    initial begin
        $display("Start of Test.");
        $dumpfile("comb_logic.vcd");
        $dumpvars(0, project4_test);
        $display("End of Test.");
    end
      
endmodule

and here are the errors:

./project4.v:29: error: Unable to bind wire/reg/memory `CDnot' in `tb_combLogic.uut'
./project4.v:29: error: Unable to elaborate r-value: ((AnotCnotD)|(CDnot))|(ACnotDnot)
project4_test.v:31: error: Unable to bind wire/reg/memory `project4_test' in `tb_combLogic'
3 error(s) during elaboration.

score 0 · Accepted Answer · answered Mar 04 '21 at 21:17

The first 2 messages are letting you know that you do not have a signal named CDnot. You likely meant BCDnot. Change:

assign F = AnotCnotD|CDnot|ACnotDnot;

to:

assign F = AnotCnotD|BCDnot|ACnotDnot;

The third message is letting you know that you do not have a signal or module instance named project4_test. One way to fix this is to change:

    $dumpvars(0, project4_test);

to:

    $dumpvars;

This will dump all signals in both modules to the VCD file. For large designs, VCD files can be huge. But, you don't need to worry about that with this code.

Problems running a test in Verilog

1 Answers1