Error: Unable to assign to unresolved wires

Question

I wrote a code for a bidirectional counter which works as an up counter if parameter updown=1 and down counter otherwise on EDAplayground using icarus verilog as my simulator:

module upctr(
  output reg [3:0] num,
  input clock
);
  
  always@(posedge clock)
    begin
      if(num!=4'd9)
        num<= num+4'd1;
      else
        num<= 4'd0;
    end
endmodule

module downctr(
  output reg [3:0] num,
  input clock
);
  
  always@(posedge clock)
    begin
      if(num!=4'd0)
        num<= num-4'd1;
      else
        num<= 4'd9;
    end
endmodule

module testgenerate(
  output reg [3:0] result=4'b0000,
  input clock
);
  parameter updown = 0;
  
  generate
    if(updown)
      upctr uc(result, clock);
    else
      downctr dc(result, clock);
  endgenerate
endmodule

When I executed the code to troubleshoot it, the following error came:

design.sv:31: error: result Unable to assign to unresolved wires.
Elaboration failed
Exit code expected: 0, received: 1

Can someone please explain what this error means and how do I correct it?

toolic · Accepted Answer · 2021-12-23T14:11:23.743

When you don't understand the meaning of error messages, you can try your code on other simulators on edaplayground. With Synopsys VCS, for example:

Error-[ICPSD_INIT] Illegal combination of drivers
  Illegal combination of structural and procedural drivers.
  Variable "result" is driven by an invalid combination of structural and 
  procedural drivers. Variables driven by a structural driver cannot have any 
  other drivers.
  This variable is declared at : reg [3:0] result;
  The first driver is at :  downctr genblk1.dc(result, clock);
  The second driver is at : result = 4'b0;

To fix it, change:

output reg [3:0] result=4'b0000,

to:

output [3:0] result,

A more common approach to initializing a counter is to add a separate reset input signal to your design, then drive it from your testbench. There are many examples, such as this one.

score -1 · Answer 2 · answered Dec 19 '21 at 07:39

-1

There is an issue with your test bench. A test bench is supposed to be a top-level entity which generates the required stimuli and records the results of its sub-modules. Hence you must generally not have a port list in the testbench, declare inputs as reg and outputs as wire. Try the below changes, It works for me.

`timescale 1ns/1ps

module testgenerate();
 parameter updown = 0;

 reg clock;
 wire [3:0] result;

 initial
  begin
   clock = 1'd0;
   $monitor(result); //This will capture and print any changes to result.
  end

always
#5 clock = ~clock; //Considered a clock with period 10ns.

generate
 if(updown)
  upctr uc(result, clock);
 else
  downctr dc(result, clock);
endgenerate
endmodule

answered Dec 19 '21 at 07:39

Pradyuman Bissa

171
1
9

Appreciate your comment but I didn't try to write a testbench here. I tried to write a design module. So if you can clarify why such error can occur in a design module, I'll be really grateful. – KaBe2003 Dec 19 '21 at 08:15
Ohh well in that case drop the `reg` when declaring `output [3:0]result` and also remove the initialization for it, Simply put `output [3:0] result` – Pradyuman Bissa Dec 19 '21 at 08:28

Error: Unable to assign to unresolved wires

2 Answers2