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I was trying to make a UART transmitter with baud rate 9600 on EDA playground using icarus verilog as my simulator. Here is my code:

`timescale 1s/1us

module UART_9600_8N1(
  output reg trans,
  input [7:0] bitsin
);
  reg [9:0] storagebits;
  reg state;
  integer k;
  parameter baud = 9600;
  
  initial
    begin
      storagebits <= 10'd0;
      state <= 1'd0;
      trans <= 1'd1;
    end
  
  always@(state)
    if(!state)
      begin
        #(1/baud) state <= ~state;
        #(9/baud) state <= ~state;
      end
  
  always@(state)
    if(!state)
      begin
        trans <= 1'b1;
        storagebits <= {1'b0, bitsin, 1'b1};
      end

  always@(state)
    if(state)
      begin
        #(1/baud) trans <= storagebits[0];
        for(k=1; k<10; k=k+1)
          #(1/baud) trans <= storagebits[k];
      end
endmodule

Now the testbench code:

`timescale 1s/1us

module UARTtester;
  wire transmitting;
  reg [7:0] inputbits;
  parameter testbenchbaud= 9600;
  
  UART_9600_8N1 testing (transmitting, inputbits);
  defparam testing.baud = 9600;
  
  initial
    begin
      $dumpfile("testuart.vcd");
      $dumpvars(1, UARTtester);
      #0 inputbits = 8'd0;
      while(1)
        begin
          #(10/testbenchbaud) inputbits <= inputbits+8'd1;
        end
      #1 $finish;
    end
endmodule

When I tried to execute the code and observe the graph of the output, the following came:

[2021-12-19 05:28:45 EST] iverilog '-Wall' '-g2012' design.sv testbench.sv  && unbuffer vvp a.out  
VCD info: dumpfile testuart.vcd opened for output.
Finding VCD file...
./testuart.vcd
[2021-12-19 05:28:47 EST] Opening EPWave...
Error launching EPWave: [Could not parse file: $timescale not found in the header.]. Could not load './testuart.vcd'
Done

Can someone please tell where I went wrong and what I can do to rectify the error? Any help is appreciated.

toolic
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KaBe2003
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1 Answers1

1

I agree that that is not a very helpful error message.

When you use the Cadence simulator on edaplayground, you get a slightly more helpful error message:

Execution interrupted or reached maximum runtime.

Your testbench has an infinite loop which prevents the simulation from ending. To fix it, you change:

while(1)

to:

repeat (1000)

This allows the simulation to end gracefully.

However, your delay expression is odd: #(10/testbenchbaud). This resolves to 10/9600, which is an integer division resulting in 0. When you run the simulation, you do not get any delays. It behaves like:

#(0) inputbits <= inputbits+8'd1;

You probably expected delays of about 104us. One way to fix that is to use floating point division. Use a decimal point with the constant: 10.0. Change:

      #(10/testbenchbaud) inputbits <= inputbits+8'd1;

to:

      #(10.0/testbenchbaud) inputbits <= inputbits+8'd1;

You have a similar problem in your design: #(1/baud), etc.

Use:

#(1.0/baud)
toolic
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