1

Waveform from the gtkwave

For my code, I want if the register 'gen_reg1' is not empty, the flag 'reg_file_empty' is set to 0. If the 'gen_reg19' is not empty, the flag 'reg_file_full' is set to 1. But the waveform is not changing as I want. I just wonder how to fix it

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        gen_reg1  <='bx;  
        gen_reg2  <='bx;  
        gen_reg3  <='bx;  
        gen_reg4  <='bx;  
        gen_reg5  <='bx;
        gen_reg6  <='bx;  
        gen_reg7  <='bx;  
        gen_reg8  <='bx;  
        gen_reg9  <='bx;
        gen_reg10 <='bx;
        gen_reg11 <='bx;
        gen_reg12 <='bx;
        gen_reg13 <='bx;
        gen_reg14 <='bx;
        gen_reg15 <='bx;
        gen_reg16 <='bx;
        gen_reg17 <='bx;
        gen_reg18 <='bx;
        gen_reg19 <='bx;
        gen_reg20 <='bx;
        reg_file_full  <= 1'b0;
        reg_file_empty <= 1'b1;
    end
    else if (activa_s2f_begin & (~reg_file_full)) begin
        gen_reg1  <= activa_s2f12  [31: 0];
        gen_reg2  <= activa_s2f12  [63:32];
        gen_reg3  <= activa_s2f34  [31: 0];  
        gen_reg4  <= activa_s2f34  [63:32];  
        gen_reg5  <= activa_s2f56  [31: 0];
        gen_reg6  <= activa_s2f56  [63:32];  
        gen_reg7  <= activa_s2f78  [31: 0];  
        gen_reg8  <= activa_s2f78  [63:32];  
        gen_reg9  <= activa_s2f910 [31: 0];
        gen_reg10 <= activa_s2f910 [63:32];
        gen_reg11 <= activa_s2f1112[31: 0];
        gen_reg12 <= activa_s2f1112[63:32];
        gen_reg13 <= activa_s2f1314[31: 0];
        gen_reg14 <= activa_s2f1314[63:32];
        gen_reg15 <= activa_s2f1516[31: 0];
        gen_reg16 <= activa_s2f1516[63:32];
        gen_reg17 <= activa_s2f1718[31: 0];
        gen_reg18 <= activa_s2f1718[63:32];
        gen_reg19 <= activa_s2f1920[31: 0];
        gen_reg20 <= activa_s2f1920[63:32];
    end
end

always @(posedge clk or negedge rst_n) begin
    if (gen_reg1  != 'bx) reg_file_empty <= 1'b0;
    if (gen_reg19 != 'bx) reg_file_full  <= 1'b1;
end

// code

module gen_reg(
    input        clk               ,
    input        rst_n             ,
    //input [63:0] activa_sram2file  ,
    input [31:0] ls2file           , //load/store to general register file
    input [31:0] alu2file          , // alu to general register file
    input [63:0] activa_s2f12      , // input from sram to reg file for reg 1 and 2
    input [63:0] activa_s2f34      ,
    input [63:0] activa_s2f56      ,
    input [63:0] activa_s2f78      ,
    input [63:0] activa_s2f910     ,
    input [63:0] activa_s2f1112    ,
    input [63:0] activa_s2f1314    ,
    input [63:0] activa_s2f1516    ,
    input [63:0] activa_s2f1718    ,
    input [63:0] activa_s2f1920    ,
    input        activa_s2f_begin  , // FLAG, begin to load the data from sram to general register file
    input        activa_f2v_begin  , // FLAG, begin to move the data from general register file to vpu
    // [only when finish the calculation in vpu, the new data move again.
    // therefore, there should a output signal from vpu to gen_reg]
    output reg [63:0] activa_file2vpu
);

reg [31:0] gen_reg1,  gen_reg2,  gen_reg3,  gen_reg4,  gen_reg5 ;
reg [31:0] gen_reg6,  gen_reg7,  gen_reg8,  gen_reg9,  gen_reg10;
reg [31:0] gen_reg11, gen_reg12, gen_reg13, gen_reg14, gen_reg15;
reg [31:0] gen_reg16, gen_reg17, gen_reg18, gen_reg19, gen_reg20;

reg reg_file_full; // flag for the general register file full
reg reg_file_empty; 

//********************************************************/
// activation input from sram to general register file   */
//********************************************************/

//********************************************************/
//* Do the parallel to series by counter                 */
//* counter number is 10                                 */
//********************************************************/
// reg  [3:0] counter;                                  
                                            
// always @(posedge clk or negedge rst_n) begin         
//     if (~rst_n) counter <= 'd0;         
//     else if (activa_s2f_begin) begin                 
//         if (counter == 'd10) counter <= 'd0;          
//         else                 counter <= counter + 1;  
//     end                                              
// end                                                  
//********************************************************/

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        gen_reg1  <='bx;  
        gen_reg2  <='bx;  
        gen_reg3  <='bx;  
        gen_reg4  <='bx;  
        gen_reg5  <='bx;
        gen_reg6  <='bx;  
        gen_reg7  <='bx;  
        gen_reg8  <='bx;  
        gen_reg9  <='bx;
        gen_reg10 <='bx;
        gen_reg11 <='bx;
        gen_reg12 <='bx;
        gen_reg13 <='bx;
        gen_reg14 <='bx;
        gen_reg15 <='bx;
        gen_reg16 <='bx;
        gen_reg17 <='bx;
        gen_reg18 <='bx;
        gen_reg19 <='bx;
        gen_reg20 <='bx;
        reg_file_full  <= 1'b0;
        reg_file_empty <= 1'b1;
    end
    else if (activa_s2f_begin & (~reg_file_full)) begin
        gen_reg1  <= activa_s2f12  [31: 0];
        gen_reg2  <= activa_s2f12  [63:32];
        gen_reg3  <= activa_s2f34  [31: 0];  
        gen_reg4  <= activa_s2f34  [63:32];  
        gen_reg5  <= activa_s2f56  [31: 0];
        gen_reg6  <= activa_s2f56  [63:32];  
        gen_reg7  <= activa_s2f78  [31: 0];  
        gen_reg8  <= activa_s2f78  [63:32];  
        gen_reg9  <= activa_s2f910 [31: 0];
        gen_reg10 <= activa_s2f910 [63:32];
        gen_reg11 <= activa_s2f1112[31: 0];
        gen_reg12 <= activa_s2f1112[63:32];
        gen_reg13 <= activa_s2f1314[31: 0];
        gen_reg14 <= activa_s2f1314[63:32];
        gen_reg15 <= activa_s2f1516[31: 0];
        gen_reg16 <= activa_s2f1516[63:32];
        gen_reg17 <= activa_s2f1718[31: 0];
        gen_reg18 <= activa_s2f1718[63:32];
        gen_reg19 <= activa_s2f1920[31: 0];
        gen_reg20 <= activa_s2f1920[63:32];
    end
end

always @(posedge clk or negedge rst_n) begin
    if (gen_reg1  != 'bx) reg_file_empty <= 1'b0;
    if (gen_reg19 != 'bx) reg_file_full  <= 1'b1;
end


//********************************************************/
// activation output from general register file to vpu   */
//********************************************************/

// counter to count the number of the activa_f2v_begin
                                 
reg activa_f2v_begin_1; //activa_f2v_begin_2;
always @(posedge clk or negedge rst_n)begin
    activa_f2v_begin_1 <= activa_f2v_begin;
    // activa_f2v_begin_2 <= activa_f2v_begin_1;
end

wire activa_f2v_begin_pos = (activa_f2v_begin)&(~activa_f2v_begin_1);

reg  [3:0] counter_flag; 

always @(posedge clk or negedge rst_n) begin         
    if (~rst_n) counter_flag <= 'd0;         
    else if (activa_f2v_begin_pos) begin                 
        if (counter_flag == 11) counter_flag <= 'd0;          
        else                    counter_flag <= counter_flag + 1;  
    end                                              
end                                                  
//********************************************************/

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        gen_reg1  <='bx;  
        gen_reg2  <='bx;  
        gen_reg3  <='bx;  
        gen_reg4  <='bx;  
        gen_reg5  <='bx;
        gen_reg6  <='bx;  
        gen_reg7  <='bx;  
        gen_reg8  <='bx;  
        gen_reg9  <='bx;
        gen_reg10 <='bx;
        gen_reg11 <='bx;
        gen_reg12 <='bx;
        gen_reg13 <='bx;
        gen_reg14 <='bx;
        gen_reg15 <='bx;
        gen_reg16 <='bx;
        gen_reg17 <='bx;
        gen_reg18 <='bx;
        gen_reg19 <='bx;
        gen_reg20 <='bx;
        reg_file_full  <= 1'b0;
        reg_file_empty <= 1'b1;
    end
    else if (counter_flag == 1) begin
        activa_file2vpu <= {gen_reg1, gen_reg2};
        reg_file_full  <= 1'b0;
    end
    else if (counter_flag == 2) begin
        activa_file2vpu <= {gen_reg3, gen_reg4};
    end
    else if (counter_flag == 3) begin
        activa_file2vpu <= {gen_reg5, gen_reg6};
    end
    else if (counter_flag == 4) begin
        activa_file2vpu <= {gen_reg7, gen_reg8};
    end
    else if (counter_flag == 5) begin
        activa_file2vpu <= {gen_reg9, gen_reg10};
    end
    else if (counter_flag == 6) begin
        activa_file2vpu <= {gen_reg11, gen_reg12};
    end
    else if (counter_flag == 7) begin
        activa_file2vpu <= {gen_reg13, gen_reg14};
    end
    else if (counter_flag == 8) begin
        activa_file2vpu <= {gen_reg15, gen_reg16};
    end
    else if (counter_flag == 9) begin
        activa_file2vpu <= {gen_reg17, gen_reg18};
    end
    else if (counter_flag == 10) begin
        activa_file2vpu <= {gen_reg19, gen_reg20};
    end
    else if (counter_flag == 11) begin
        reg_file_empty <= 1'b1;
    end
end

endmodule

`timescale 1ps/1ps
`include "../rtl/gen_reg.v"

module gen_reg_tb();
    reg         clk;
    reg         rst_n;
    //reg [63:0]  activa_sram2file;
    reg [31:0]  ls2file; 
    reg [31:0]  alu2file; 
    reg [63:0]  activa_s2f12      ;
    reg [63:0]  activa_s2f34      ;
    reg [63:0]  activa_s2f56      ;
    reg [63:0]  activa_s2f78      ;
    reg [63:0]  activa_s2f910     ;
    reg [63:0]  activa_s2f1112    ;
    reg [63:0]  activa_s2f1314    ;
    reg [63:0]  activa_s2f1516    ;
    reg [63:0]  activa_s2f1718    ;
    reg [63:0]  activa_s2f1920    ;
    reg         activa_s2f_begin; 
    reg         activa_f2v_begin;
    wire [63:0] activa_file2vpu;


gen_reg u_gen_reg(
    .clk             (clk),
    .rst_n           (rst_n),
    //.activa_sram2file(activa_sram2file),
    .ls2file         (ls2file), 
    .alu2file        (alu2file), 
    .activa_s2f12    (activa_s2f12)   ,
    .activa_s2f34    (activa_s2f34)   ,
    .activa_s2f56    (activa_s2f56)   ,
    .activa_s2f78    (activa_s2f78)   ,
    .activa_s2f910   (activa_s2f910)   ,
    .activa_s2f1112  (activa_s2f1112)   ,
    .activa_s2f1314  (activa_s2f1314)   ,
    .activa_s2f1516  (activa_s2f1516)   ,
    .activa_s2f1718  (activa_s2f1718)   ,
    .activa_s2f1920  (activa_s2f1920)   ,
    .activa_s2f_begin(activa_s2f_begin), 
    .activa_f2v_begin(activa_f2v_begin),
    .activa_file2vpu (activa_file2vpu)
);


//********************************************************/
//* Generate the wave                                    */
//********************************************************/
initial begin             //******************************/
  $dumpfile ("wave.vcd"); //******************************/
  $dumpvars;              //******************************/
end                       //******************************/
//********************************************************/

initial begin                                                  
    clk = 0;
    forever #5 clk = ~clk;               
end

initial begin
    rst_n = 0;
    activa_s2f_begin = 'b0;
    activa_f2v_begin = 'b0;
    #7 
    rst_n = 1;

    // Test for the Activation Input
    activa_s2f_begin = 'b1;
    activa_s2f12 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF;
    #10
    activa_s2f34 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF;
    #10
    activa_s2f56   = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f78   = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f910  = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f1112 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f1314 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f1516 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f1718 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    #10
    activa_s2f1920 = 'h0123_4567_89AB_CDEF_0123_4567_89AB_CDEF  ;
    
    //Test for the Activation Output
    #100
    repeat (30) begin
        #50 activa_f2v_begin = 1;
        #10 activa_f2v_begin = 0;
    end

    #100 $finish;
end
endmodule

I just wonder how to fix it

toolic
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Shibo Dang
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1 Answers1

0

reg_file_empty is always 1 because (gen_reg1 != 'bx) is never true. You use the wrong comparison operator. You need to change != to !==, the case inequality operator, which correctly compares against unknown values (x). Refer to IEEE Std 1800-2017, section 11.4.5 Equality operators.

It is better to also specify the width of the signal in the comparison (32).

always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        reg_file_full  <= 1'b0;
        reg_file_empty <= 1'b1;
    end else begin
        if (gen_reg1  !== {32{1'bx}}) reg_file_empty <= 1'b0;
        if (gen_reg19 !== {32{1'bx}}) reg_file_full  <= 1'b1;
    end
end

Also, you should make all assignments to reg_file_empty within the same always block. Remove it from the big always block.

With this change, you will see reg_file_empty go to 0.

toolic
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