Verilog code compiles without error but no output

Question

module encoder (op, in, clock, reset);
     
     //$display("We are in initial procedural block");

     input [15:0] in;
     input clock, reset;
     output [3:0] op;

     wire [15:0] in;
     wire clock, reset;

     reg [3:0] op;

     always @ ( posedge clock)
     begin
          $display("We are in initial procedural block");

          if (reset)
          begin
               $display("we are in the reset condition");
               op = 0;
          end
          else 
          begin
               case(in)
                    16'h0002: #1 op = 4'b0001;
                    16'h0004: #1 op = 4'b0010; 
                    16'h0008: #1 op = 4'b0011;
                    16'h0010: #1 op = 4'b0100;
                    16'h0012: #1 op = 4'b0101;
                    16'h0014: #1 op = 4'b0110; 
                    16'h0018: #1 op = 4'b0111;
                    16'h0020: #1 op = 4'b1000; 
                    16'h0022: #1 op = 4'b1001;
                    16'h0024: #1 op = 4'b1010; 
                    16'h0028: #1 op = 4'b1011;
                    16'h0030: #1 op = 4'b1100;
                    16'h0032: #1 op = 4'b1101;
                    16'h0034: #1 op = 4'b1110; 
                    16'h0038: #1 op = 4'b1111;
                    16'h0040: #1 op = 4'b0000;
                    default : $display("DEFAULT!!!");
               endcase 
          end
     end
endmodule

module encoder_tb;

     input in, reset, clock;
     output op;

     reg [15:0] in = 16'h0000;
     reg reset, clock;
     wire [3:0] op;

     //internal variable
     reg [15:0] incremental_value = 16'h0002;

     initial
     begin
          $monitor("time = %g,\tclock = %d,\tin = %h,\top = %b", 
                          $time,      reset,       in,       op );

          $display("We are in initial procedural block");

          in    = 0;
          reset = 0;
          clock = 0;
          op    = 0;
      #1  clock = !clock; 
      #10 reset = !reset;
      #5  in    = in + incremental_value; 
          #100 $finish;
     end

     always 
     begin
     #1  clock = !clock; 
     #10 reset = !reset;
     #5  in    = in + incremental_value; 
     end 

     encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );

     // Waveform Generation
     initial
     begin
          $dumpfile("encoder.vcd");
          $dumpvars(0,op,in,clock,reset);
     end
   
endmodule

I have tried to create a 16-bit input to 4-bit output encoder. I am able to compile my code without any errors, but after [iverilog encoder_tb.v -o encoder] & [vvp encoder vcd] commands, it gives me nothing even though I have given $monitor and a few $display statements everywhere I could think of. I am not able to debug this.

Display statements are not really sufficient for debugging any complex RTL. You should look into using a waveform viewer program. *Xilinx ISE webpack* is a useful and free one that comes to mind, or possibly *iVerilog* — Tim, Nov 28 '13 at 00:13
@Tim - i am have included / tried to generate the waveform using GTKwave using commands $dumpfile and $dumpvars but i am not able to generate any waveforms. Thanks — user3043882, Nov 28 '13 at 00:22

toolic · Accepted Answer · 2020-12-03T20:12:38.497

I get compile errors with your code on 2 different simulators (VCS and Incisive). Perhaps your simulator compiles the code, but then does not simulate properly because of the poor coding.

The encoder_tb module has input and output statements but no port list.

The encoder_tb module has a recursive instance of itself.

You make a procedural assignment to a wire (op).

When I make these changes, I get some output:

module encoder (op, in, clock, reset);
     
     //$display("We are in initial procedural block");

     input [15:0] in;
     input clock, reset;
     output [3:0] op;

     wire [15:0] in;
     wire clock, reset;

     reg [3:0] op;

     always @ ( posedge clock)
     begin
          $display("We are in initial procedural block");

          if (reset)
          begin
               $display("we are in the reset condition");
               op = 0;
          end
          else 
          begin
               case(in)
                    16'h0002: #1 op = 4'b0001;
                    16'h0004: #1 op = 4'b0010; 
                    16'h0008: #1 op = 4'b0011;
                    16'h0010: #1 op = 4'b0100;
                    16'h0012: #1 op = 4'b0101;
                    16'h0014: #1 op = 4'b0110; 
                    16'h0018: #1 op = 4'b0111;
                    16'h0020: #1 op = 4'b1000; 
                    16'h0022: #1 op = 4'b1001;
                    16'h0024: #1 op = 4'b1010; 
                    16'h0028: #1 op = 4'b1011;
                    16'h0030: #1 op = 4'b1100;
                    16'h0032: #1 op = 4'b1101;
                    16'h0034: #1 op = 4'b1110; 
                    16'h0038: #1 op = 4'b1111;
                    16'h0040: #1 op = 4'b0000;
                    default : $display("DEFAULT!!!");
               endcase 
          end
     end
endmodule

module encoder_tb;

//     input in, reset, clock;
//     output op;

     reg [15:0] in = 16'h0000;
     reg reset, clock;
     wire [3:0] op;

     //internal variable
     reg [15:0] incremental_value = 16'h0002;

     initial
     begin
          $monitor("time = %g,\tclock = %d,\tin = %h,\top = %b", 
                          $time,      reset,       in,       op );

          $display("We are in initial procedural block");

          in    = 0;
          reset = 0;
          clock = 0;
//          op    = 0;
      #1  clock = !clock; 
      #10 reset = !reset;
      #5  in    = in + incremental_value; 
          #100 $finish;
     end

     always 
     begin
     #1  clock = !clock; 
     #10 reset = !reset;
     #5  in    = in + incremental_value; 
     end 

//     encoder_tb test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );
     encoder test_bench ( .op(op), .in(in), .clock(clock), .reset(reset) );

     // Waveform Generation
     initial
     begin
          $dumpfile("encoder.vcd");
          $dumpvars(0,op,in,clock,reset);
     end
   
endmodule

Outputs:

We are in initial procedural block
time = 0,       clock = 0,      in = 0000,      op = xxxx
We are in initial procedural block
DEFAULT!!!
time = 16,      clock = 0,      in = 0004,      op = xxxx
We are in initial procedural block
time = 18,      clock = 0,      in = 0004,      op = 0010
time = 27,      clock = 1,      in = 0004,      op = 0010
time = 32,      clock = 1,      in = 0006,      op = 0010
time = 43,      clock = 0,      in = 0006,      op = 0010
time = 48,      clock = 0,      in = 0008,      op = 0010
We are in initial procedural block
time = 50,      clock = 0,      in = 0008,      op = 0011
time = 59,      clock = 1,      in = 0008,      op = 0011
time = 64,      clock = 1,      in = 000a,      op = 0011
time = 75,      clock = 0,      in = 000a,      op = 0011
time = 80,      clock = 0,      in = 000c,      op = 0011
We are in initial procedural block
DEFAULT!!!
time = 91,      clock = 1,      in = 000c,      op = 0011
time = 96,      clock = 1,      in = 000e,      op = 0011
time = 107,     clock = 0,      in = 000e,      op = 0011
time = 112,     clock = 0,      in = 0010,      op = 0011
We are in initial procedural block
time = 114,     clock = 0,      in = 0010,      op = 0100

Verilog code compiles without error but no output

1 Answers1