Error: 'a' has already been declared in this scope

Question

I have made two files (or_gate and or_gate_tb) in vscode, and I am trying to run using the following command on the macOS terminal:

iverilog -o or_gate.vvp or_gate_tb.v

This is my result, and I can not find anything wrong with my code:

./or_gate.v:2: error: 'a' has already been declared in this scope.
./or_gate.v:1:      : It was declared here as a net.
./or_gate.v:3: error: 'b' has already been declared in this scope. 
./or_gate.v:1:      : It was declared here as a net.
./or_gate.v:5: syntax error
./or_gate.v:5: error: Syntax error in continuous assignment
or_gate_tb.v:47: syntax error
or gate tb.v:47: error: Malformed statement

Below is my testbench file:

`include "or_gate.v"
module or_gate_tb();

reg a_tb;
reg b_tb;

wire c_tb;

/// here the test bench register values go into input of or_gate module inputs
or_gate a1(.a(a_tb),
    .b(b_tb), 
    .c(c_tb) );

// truth table of or gate
initial begin
        //row1 of truth table
        // start at t ~ 0 
        a_tb = 0;
        b_tb = 0;
        #50
       
       //row2 of truth table
       // start at t ~ 50
        a_tb = 0;
        b_tb = 1;
        #50

        //row1 of truth table
        // start at t ~ 100;
        a_tb = 1;
        b_tb = 0;
        #50

        //row1 of truth table
        // start at t ~ 150;
        a_tb = 1;
        b_tb = 1;
        #50

        #500 $finish;

    
end

initial begin 
    $dumpfile("or_gate_tb.vcd")
    $dumpvars(0,or_gate_tb);
end

endmodule

I am not sure what I am doing wrong. I have run the iverilog command in both terminals, and I am getting the same result.

Answer 1

There is no need to declare the 3 or_gate module ports as wire. Delete the wire lines:

module or_gate (input a, input b, output c);
    assign c = a | b;
endmodule

That fixes the errors on lines 1-5.

To fix the error on line 47 in the testbench, add a semicolon after the $dumpfile statement:

initial begin 
    $dumpfile("or_gate_tb.vcd");
    $dumpvars(0,or_gate_tb);
end

Answer 2

You are mixing up two different styles of port declarations, which is illegal syntax.

The older (referred to as non-ANSI style) port declarations list just the port names in the module header defining a positional order. That is followed by the directions and data types appearing in the module body.

module or_gate (a, b, c); // order matters here
  output c;
  wire c;
  input a;
  wire a;
  input b;
  wire b;
  
    assign c = a | b;
endmodule

The newer (from 2001) and recommended port declarations syntax (referred to as ANSI-stle) puts all port information into the module header. The key syntax that distinguishes between the two styles is starting out with a port direction keyword.

module or_gate (input wire a, 
               input wire b,
               output wire c);
    assign c = a | b;
endmodule

Note that in both styles, wire is implicit and can be omitted.