2

I have done a error control code in verilog, in that I got decoded data with some delay of 18000 ns. I need to compare the decoded data with the original data but my original data start some 100 ns, so how to do comaparision of this two signals.

How to delay my input data in verilog and that should be synthesizable?

I need to implement this is hardware.

Dovydas Šopa
  • 2,282
  • 8
  • 26
  • 34
meghana MN
  • 17
  • 3
  • I think you need to may need to correct your basics, refer [here](https://embeddedmicro.com/tutorials/mojo/writing-test-benches) – Emman May 29 '17 at 09:02
  • 2
    Usually testbenches aren't synthesisable? Anyway, for a delay in hardware, you use a counter which updates on every positive edge of your clock. In this way you can keep a track of delay by counting the number of cycles. – Rahul Behl May 29 '17 at 09:29
  • 1
    Delays can't be synthesized. After the backend process, the delays will be included by the standard cell delays and routing net delays. – Karan Shah May 29 '17 at 09:58
  • How about generating delays using counters? Those should be synthesizable. – Rahul Behl May 29 '17 at 14:59

2 Answers2

1

One option is to instantiate one or more buffer cells manually. For that, you will need to know the cell name regarding your tech library and your RTL code will be tech dependent. If you don't want this, you can also create your own buffer module (e.g. with inverters) and can use it.

Here is an example for Verilog instantiation. BUFX1 is the cell name in an arbitrary library.

BUFX1 my_buffer (.in(my_signal), .out(my_delayed_signal));

Normally synthesis and P&R tools optimize out this cell, but you can tell the tool that you want to keep it. The example constraint below is in Synopsys Design Constraints (SDC) format. Most of the tool vendors support it.

set_dont_touch <path to my_buffer>

You should be aware of that the delay of the cell will be different for each corner (e.g. slow, typical, fast). So the delay is not constant, but in a range.

0

A synchronous way of generating a delay would be to use a shift register which will shift the data you want to compare by as many clock cycles as needed. With this method, or with a counter as proposed in the commentaries, you should reach a delay close to the target.

However, if you clock period is not suitable for a shift register, you can generate delay by semi-manually buffering the signal:

Use your synthesis tool to generate the wanted delay. For example with Synopsys' Design Compiler: set_min_delay delay_value_in_ns -from startpoint -to endpoint will indicate the tool that to be correct you want at least delay_value_in_ns between startpoint and endpoint. You can also set a value to constrain the max value: set_max_delay

These constraints will have to be forwarded to further flow steps like place and route to keep the correct delay.

Krouitch
  • 596
  • 3
  • 13