SVerilog can't compile in VSCode

Question

Here are the cods (1st one is the testbench and the second one the module)

`timescale 1ns/1ps 
`include "not_example1.sv" 

module testbench;
    parameter BITS = 4;
    logic [BITS-1:0] s_in;
    logic [BITS-1:0] s_model_outs; 

not_example1     #(.NUM(BITS))   not_model    (.i_a(s_in), .o_y1(s_model_outs));
    
initial
    begin 
            $dumpfile("signals.vcd");  
                                        
            $dumpvars(0,testbench);     

        s_in = '0;
        #1  
            s_in = '1;
        #1  s_in = '0;
        #1  s_in = '1;
        
        #1 

            $finish;
        
        end
endmodule

Module

module not_example1 (i_a, o_y1);

    parameter NUM = 4;
    input  logic [NUM-1:0] i_a;
output logic [NUM-1:0] o_y1;

always_comb
begin
    o_y1 = ~ i_a;
end

endmodule

Basically the error is that I can't compile the testbench program. I'm writting everything in SystemVerilog (.sv). The message I get is :

enter image description here

I don't know what is this -g2005-sv. Is it something I should download ? Because the code to compile .sv file is correct I guess.

what is vsc? how did you compile? which errors did you see? Do not insert links to code, insert the code itself. Read this: https://stackoverflow.com/help/how-to-ask — Serge, Oct 30 '22 at 00:58
Your code is a syntactically correct 'system verilog' code. -g2005 runs iverilog in a simple verilog mode. So, it will not be compatible with your program. To run in system verilog mode you need -g2012. But even in this case icarus does not support the full extend of system verilog. — Serge, Oct 30 '22 at 11:25

Serge · Accepted Answer · 2022-10-30T11:46:54.607

Your code is a syntactically correct 'system verilog' code. However, iverilog is not a good tool to compile it.

-g2005 runs iverilog in a verilog 2K mode. It does not understand any of SV constructs. So, it will not be compatible with your program. To run in system verilog mode you need -g2012. But even in this case, icarus does not support a lot of system verilog constructs. In your case it had trouble with the not_example1 module. I tried to modify it to make compatible with iverilog (10.0) -g2012 in eda-playground.

module not_example1 (i_a, o_y1);
  parameter NUM = 4;
  input  [NUM-1:0] i_a; // logic did not work here
  output reg [NUM-1:0] o_y1; // logic did not work here

always @* // always_comb did not work
begin
    o_y1 = ~ i_a;
end

endmodule

EDA playground only has version 10 installed. So, you can try 11 on your own it might be more tolerant to your original constructs.

I've compiled it with the original code using -g2005 and I guess it worked ? Because in the gtkwave it showed everything alight except one thing which was parameter. Because on gtkwave it showed that the NUM[31:0] which I don't underestand I can edit the post but I don't know if it will be helpfull Also I use 12.0 iverilog — user331990, Oct 30 '22 at 12:12

SVerilog can't compile in VSCode

1 Answers1