Are recursive functions in Verilog synthesizable?

Question

Functions which do not contain any delay assignments are synthesizable, hence all synthesized functions are combinational in nature. Will the function still remain synthesizable if we have a recursive call?

Taking an example of Factorial function (automatic). This functions is present in a state machine. Every time the state is activated, the function would return the value to a register.

Will this function synthesize?

Answer 1

Yes, recursive function can be synthesizable, but only if the depth of recursion can be determined at compile time. That usually means the arguments to each top-level call to the function are constants. Like any other loop, a synthesis tool needs to have a fixed number of iterations to know exactly how much hardware logic needs to be allocated.