Errors in benchmark code

Question

Flipflop structural code and test bench code

I don't know where I have made a mistake. I am getting few errors in the output.

`timescale 1ns/1ps

module t_ff (
input clk,t,rst_n,
output reg q);

    always@(posedge clk ,negedge rst_n)
    begin
        if (!rst_n)
            q <= 1'b0;
        else if(t)
            q <= ~q;
        else
            q <= q;
    end

endmodule

@@@test bench@@@@

`timescale 1ns/1ps

module tb_tff;
reg RST_n, CLK,T;
wire Q;

t_ff TFF (.clk(CLK) ,.rst_n(RST_n) ,.q( Q ),.t(T));

 initial begin
 RST_n = 1'b0;
 CLK =1'b0;
 T =1'b0;
  #5 RST_n = 1'b1;
  #13 RST_n = 1'b0;
 #7 RST_n = 1'b1;
  #45 $finish;
 end

 always #3 CLK = ~CLK;
 always #6 T = ~T;

always @(posedge CLK ,negedge RST_n)
  $strobe("time =%0t \t INPUT VALUES \t T =%b RST_n =%b \t OUTPUT VALUES 
Q=%d",$time,T,RST_n,Q);

endmodule

Getting the errors like this:

Error-[V2KS] Verilog IEEE 1364-2000 syntax used

TFlipflop.v, 4 Verilog 2000 IEEE 1364-2000 syntax used : Combined port and type declaration. Please compile with +v2k to support this construct.

Error-[V2KS] Verilog IEEE 1364-2000 syntax used

TFlipflop.v, 4 Verilog 2000 IEEE 1364-2000 syntax used : Ansi style port declaration. Please compile with +v2k to support this construct.

Error-[V2KS] Verilog IEEE 1364-2000 syntax used

TFlipflop.v, 6 Verilog 2000 IEEE 1364-2000 syntax used : Comma separated sensitivity lists. Please compile with +v2k to support this construct.

Parsing design file 'test_TFlipflop.v'

Error-[V2KS] Verilog IEEE 1364-2000 syntax used

test_TFlipflop.v, 21 Verilog 2000 IEEE 1364-2000 syntax used : Comma separated sensitivity lists. Please compile with +v2k to support this construct.

4 errors CPU time: .036 seconds

What simulator and version are you using? Sounds like you need to add `+v2k` to your compiler options. Modern simulators have enabled by default. — Greg, Nov 17 '15 at 04:29

score 0 · Answer 1 · answered Nov 17 '15 at 04:28

Seems that your simulator needs an update. Try a newer version. All these are valid ANSI styles. Following are the error reasons and some workarounds:

Error-[V2KS] Verilog IEEE 1364-2000 syntax used
TFlipflop.v, 4
Verilog 2000 IEEE 1364-2000 syntax used : Combined port and type 
 declaration.

I guess the error says output reg q is not valid, even though it is a valid ANSI style. So, do something like this:

module t_ff (input clk,t,rst_n,output q);
reg q;

// Alternate Non-ANSI style
module t_ff (clk,t,rst_n,q);
input clk,t,rst_n;
output q;
reg q;

Next is :

Error-[V2KS] Verilog IEEE 1364-2000 syntax used
TFlipflop.v, 6
Verilog 2000 IEEE 1364-2000 syntax used : Comma separated sensitivity lists.

This is also valid synthesizable declaration, either use as follows, in both testbench and design:

always@(posedge clk or negedge rst_n) // use or

You can also add +v2k switch and try again. I've simulated your code at EDAPlayground, and works completely well.

Errors in benchmark code

1 Answers1