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Questions tagged [iverilog]

`iverilog` is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing.

iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation, and fpga for synthesis. Other target types are added as code generators are implemented.

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Alternate signals for test bench without manually typing out all times in iverilog

I am writing a test bench that I want to be able to have signals go high and low in a certain pattern (something like this): Currently I manually type out what I want each time to be like this: module TestExample; reg a, b, c; initial begin …
Tyler Hilbert
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Verilog: Implementation Using Primitive Modules vs. Bit-wise Operators

The textbook I'm reading implements 1-bit adders using built-in primitive modules: module yAdder1(z, cout, a, b, cin); output[0:0] z, cout; input[0:0] a, b, cin; wire[0:0] tmp, outL, outR; xor left_xor(tmp, a, b); xor…
NoName
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Verilog: How to extend the binary in a register?

What's the format for the code to sign-extend and zero-extend the binary in a register? i.e. reg[0:0] a; //a is 1-bit. reg[31:0] b, c; //b and c are 32-bits. //some code... Sign-extend a into 32-bits, add it to b, and put the result into…
NoName
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Verilog: === Operator Not Working

I have a wire: wire module3Output; In the end, I test the binary on the wire using: initial begin if (module3Output === 1) #1 $display("PASS: module3Output=%b", module3Output); else #1…
NoName
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Verilog - Nested generate for loop with multiple genvars, not possible?

I'm trying to add a second level of nesting to my generate loop in the following code, but iverilog is throwing an error that the register j is unknown: ../crc.v:119: register ``j'' unknown in crc_tb.U_crc.loop[31]. So is it possible to use multiple…
JMercer
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I get compile errors: data_out is not a valid l-value

This is the module unit... module register_unit(data_out,data_in,load,clk,rst); parameter word_size=8; output [word_size-1:0] data_out; input [word_size-1:0] data_in; input load,clk,rst; reg data_out; always@(posedge clk or negedge rst) …
Devender Bhardwaj
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iverilog syntax for include?

I'm trying to include a Verilog file (alu.v) in my main file (cpu.v). Both files are in the same directory. 'include "alu.v" module cpu(); ... ... endmodule When I try to compile it, I get the following error. cpu.v:1 syntax error I give up I…
user3044500
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Error in simple Verilog for-loop

I'm getting familiar with Verilog doing small exercises and right now I am trying to implement a linear feedback shift register. I'm trying to model the flipflop chain inside an always block using a for-loop, yet iverilog keeps giving me the error…
Jersey
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Creating a 32 bit ALU in Structural Verilog and I'm not quite sure how to implement opcodes

I have to create a 32 bit ALU in structural verilog with opcodes for AND(000), OR(001), ADD(010), SUB(110), SLT(111), and BEQ(100). I understand how each of these work individually at the gate level I'm just confused on how to use opcodes to get my…
AlexImp
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Systemverilog rule 4.7 (nondeterminism) is interpreted differently by vcs vs iverilog/modelsim

I am still a bit confused about how SystemVerilog's 2012 rule 4.7 is implemented. The rule states that in a situation like this: module test; logic a; integer cnt; initial begin cnt = 0; #100; a <= 0; a <= 1; a <= 0; a…
Marco
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Verilog code for shift and add multiplier

Good day guys, I'm created a Shift - And - Add multiplier. I'm confused on why my output is wrong and always at 85. Is it something with the Test bench ? It's working by the way. new1.v `define M ACC[0] module mult4X4 (Clk, St, Mplier, Mcand, Done,…
will
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Verilog error : Unable to bind parameter in module

I'm new to Verilog, I'd really appreciate it if someone could help me figure this error out: I'm trying to write a test bench PU_tb, which is instantiating this module: PU_conv #( .image_width ( image_width ), .image_height (…
AnnaR
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Verilog error : A reference to a wire or reg is not allowed in a constant expression

I'm new to Verilog and I would really appreciate it if someone could help me out with this error: output reg [0:image_width][image_height:0] result .... integer i, j, imageX, imageY, x, y, kernelX, kernelY; .... @(negedge ACLK) for(x = 0; x <…
AnnaR
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verilog code to find a single max value for an input that has 1000 samples values

i want to find a single max value for an input signal that has 1000 decimal values that is read from a memory once every Positive clk edge.i did the following rough code for finding max value but it didn't give me the correct max value/number please…
MR.simple
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Value changes based on clk doesn't work for random numbers

I am coding that put the value of 'd' into 'z' whenever 'clk' is changed to '1'. For example, clk=0 d= 15, z= x clk=1 d= 20, z= 20 clk=0 d= 25, z= 20 clk=1 d= 30, z= 30 it put value of 'd'…
online.0227
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