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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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#address-cells and #size-cells field in device tree overlay range property

I am trying to load a file into a stratix10 FPGA and map the FPGA busses using the embedded Hard processor, ARM running linux (Linux 5.4.23-03466-gcc83036e6a78 #1 SMP PREEMPT Wed Aug 5 10:15:00 CEST 2020 aarch64 GNU/Linux). This is done with device…
user1159290
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Quartus does not allow using a Generate block in Verilog

Pretty simple problem. Given the following code: module main( output reg [1:0][DATA_WIDTH-1:0] dOut, input wire [1:0][DATA_WIDTH-1:0] dIn, input wire [1:0][ADDR_WIDTH-1:0] addr, input wire [1:0] wren, input wire clk ); …
Kraken
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Tristate buffers in Quartus II

I need to clear up a problem with an external input to a CPLD by putting it through a tristate buffer. I know Quartus II has a tristate-buffer megafunction, but I am curious - if I simply tell it to output Z on the specific pin, will in…
shieldfoss
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Modifying DE10-nano default FPGA configuration

I am working with Linux software on DE10-nano board and I need to perform a small modification to default FPGA configuration (add pull-ups on GPIO lines). The user manual points to DE10-Nano System CD\Demonstrations\FPGA\Default as default project…
jackhab
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Can FPGA Stratix 3 memory handle large amount of data?

I need to allocate an array in FPGA of 20 elements, each of size 323 bits, but don't know if my fpga memory can handle this size. I am using an FPGA Stratix 3. I hav tried looking up on the intel website :…
Noura AIT MANSSOUR
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Why does printf with %lld return a different number than with %16x when using 64 bit (long long)?

I am accessing memory on a FPGA from a HPS running Linux and I stumbled upon a problem. { long long address_debug = *(shared_memory + i); printf("index: %i - value: %16x \n", i, address_debug); } returns the values that I…
user3637713
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CMake add_custom_command fails with bin/sh:1 : ... not found

What I want to achieve I try to set up a toolchain to compile OpenCL applications for Intel FPGAs. Therefore beneath building the C++ based host application I need to invoke the Intel OpenCL offline compiler for OpenCL kernels. This step should only…
PluginPenguin
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How to check that microprocessor is Altera Nios?

I writes some C-program code for Altera/Nios II microprocessor (uP). This code will be different with Altera Arm 9 microprocessor. So I need to write 2 different code pieces for different uP-s. How can I check in execution time which uP is present.…
Yakov
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How to add a qip file to a Quartus project generated from a Makefile

I like to have the project file untouched unless I make an active decision to add something, so I create the project file using make. The first instance of the project file is created by quartus_map and I can later add pin declarations etc using…
Bimme
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Driving bidirectional lines in Verilog

this question probably wont be explained very well and that's because I don't really understand what's happening in my design. I need to use an I2C communication bus to talk to a camera (Terasic D5M) so I tried to write one using Verilog. I only…
Student
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With ModelSim, how to update waveforms to the newest dataset?

Background : ModelSim v10.4d installed with quartus v16.0 I wrote a .do file to simulate my design with ModelSim. The steps in my .do file are: 1- vcom *.vhd : compile all sources files and testbench 2- vsim work.my_tb : load testbench for…
Cong Li
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Altera design library does not contain primary unit

I am using following altera 2008 library: library altera_2008; use altera_2008.fixed_generic_pkg.all; When running the Quartus 17.1 compiler I get following error message: Error (10481): VHDL Use Clause error at Polyfit.vhd(48): design library…
Norick
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VHDL buffer variable vs out variable

I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram…
Raul Juliao
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Memory mapped ADC on DE1-SoC using HPS (hard-core processor)

I am unable to read from or write to the AD7928 analog to digital converter (ADC) on the DE1-SoC (Rev. F) development board. I have the datasheets for the board and the ADC. I am using a mix of custom IP and pre-made hardware components. I have…
Gordon
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NIOS II c++ string does need massive memory in Hello World application

I am currently working with the quartus prime (16.1) and NIOS II eclipse tool chain. I tried to compile a simple C++ Hello World application, but I get an error like this: "onchip_memory2_nios2' overflowed by 609088 bytes" My question now is: Is…
Litschi
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