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The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be. 

`library IEEE;
USE IEEE.std_logic_1164.all;
entity case_ex_TB is end;
architecture simple_test of case_ex_TB is
--- DUT Component Declaration ---
component case_ex
    port(
    clk, rstN: IN std_logic;
    color: OUT std_logic_vector(2 downto 0));
end component;
--- Signals Declaration ---
signal rst, clock: std_logic:='0';
signal color: std_logic_vector(2 downto 0);

begin
DUT: case_ex  --- DUT instantiation ---
port map (clk => clock,
         rstN => rst,
         color => color);
--- Signal's Waves Creation ---
rst <= '1','0' after 50 ns, '1' after 2 us;
clock_crtate: process
begin
    while rst = '0' loop
        clock <= '1','0' after 50 ns;
        wait for 100 ns;
    end loop;
        clock <= '1';
        wait;
end process;
end simple_test;`
aviv yaakobi
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  • You mention Quartus-II, but what simulator are you using? You are not trying to synthesize this, are you? – Morten Zilmer Nov 18 '15 at 14:30
  • Hi Morten, i write my code with Quartus-II and after i "Start Analysis & Synthesis" i get this Error: Error (10533): VHDL Wait Statement error at case_ex_TB.vhd(26): Wait Statement must contain condition clause with UNTIL keyword. – aviv yaakobi Nov 18 '15 at 14:36
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    Synthesis is for implementation of a design in a device, and synthesis can't handle timed wait like `wait for 100 ns;`. For test bench you usually need a simulator like ModelSim. Altera has ModelSim Starter Edition in the suite, so take a look at that. – Morten Zilmer Nov 18 '15 at 14:40
  • Ok, thanks for your help. – aviv yaakobi Nov 18 '15 at 14:51

2 Answers2

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You get this error because you have set your testbench as the top-level entity in Quartus-II. The top-level entity must remain the component case_ex, and this component must contain synthesizable code.

To simulate your testbench, you must configure a testbench. Just klick on the plus-sign before "RTL Simulation" and then "Edit Settings". (Names may differ with Quartus version).

Martin Zabel
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0

Another thing you could note is that, it's necessary to put this file in as a simulation, following the path:

Assignments -> settings -> EDA tool settings -> simulation

and naturally, changing adding a testbench.

Another thing to note is that, if you want to change the top level entity, you just need to follow in Quartus:

Project -> Set as top level entity (in the file you are in)

Also, in the Project navigator, be sure that don't miss the fact that you need every single file you need in order for your program to work.

João Víctor Melo
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