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Questions tagged [intel-fpga]

Intel FPGA - formally known as Altera - which is wholly owned subsidiary of Intel, is a major brand of Field Programmable Gate Arrays (FPGA).

Intel FPGA is a company part of Intel creating FPGAs and CPLD. It is a Xilinx competitor. Famous associated name are:

  • Stratix
  • Cyclone
  • Arria
  • MAX

It also offers intellectual properties like Nios II Processor, Hardware development programs like Quartus, software development programs like Nios Embedded Software.

This link points to various trainings that are free and offered by Intel FPGA.

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Testing PCI Interface on FPGA

My boss has given a code for testing PCI express on an Altera board. The code consist of several c code files having instructions such as reading Bios, setting some registers, writing to buffers etc. My job at present is to see the functionality of…
gpuguy
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Can't infer register in Quartus II (VHDL)

This is the full code library ieee; use ieee.std_logic_1164.all; entity move_key_detector is PORT( clk : IN STD_LOGIC; done : IN STD_LOGIC; hex : IN STD_LOGIC_VECTOR(7 DOWNTO 0); up, down : out std_logic …
CppLearner
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How to Simulate PCIe Design Using BFMs? Intel PCIe_DDR Design

I am trying to simulate the reference design (PCIe_DDR4) on Terasic DE5a-Net DDR4 edition board. I want to simulate this and confirm meaningful DDR4 read/writes in ModelSim. Referring to Intel Documentation :…
baggins6000
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communication between PC and Altera through RS232 cable using VHDL and C#

I'm doing a school project where I need to pass notes (char, ascii) using a C# code in VS to an Altera card using a RS232 cable. when I'm sending a single note('A') the data goes through just fine but when I'm trying to send two notes at the same…
Omer DT8
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Verilog - output exuals to XXXXXXXX

I'm trying to design a 32-bit ALU. While simulating using Modelsim output R becomes mixed with x's and 0's like this, at time=20 the addition is calculated and at time=40, substraction is calcualted. In the ALU I'm only calling 3 modules. Adder,…
questionhead
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Quartus-FPGA: Disable Path Optimization

module path1(out, in, w0, w1, w2, w3, w4, w5, w6, w7, w8, w9); input in; output out; output w0, w1, w2, w3, w4, w5, w6, w7, w8, w9; not(w0, in); not(w1, w0); not(w2, w1); not(w3, w2); not(w4, w3); not(w5, w4); not(w6, w5); not(w7, w6); not(w8,…
zibidigonzales
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How can I prevent that DSP blocks are synthesized away if they are not connected to a top level output?

I am using an Intel Stratix 10 FPGA and Quartus Prime Pro 21.4 to develop a power test project. I cannot figure out how keep Quartus from optimizing away my DSP blocks. I want to use all 3000 DSP blocks in our FPGA so that I can see the max current…
sealenator
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Error (10028): Can't resolve multiple constant drivers and Error (10029): Constant driver

I am new to Verilog, and trying to write a traffic light code where the LED light changes after certain time. I'm keep getting on different errors while compiling. I tried to fix them by changing the arrangement, or variables in the code, but it…
Doyeon.K
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Compilation of verilog code in quartus prime takes much longer after adding block

I am attempting to make the snake game in verilog using my DEE-10 Lite and compiling using Quartus Prime (Lite Edition Version 20.1.1). The Analysis and Synthesis time takes almost 10 times longer after adding the following for loop: for (i = 0); i…
Jessey H
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The clock speed is two times faster when the clock duty cycle is 50%

I want to generate 102Hz clock on a FPGA board(the one with cyclone 3） the original clock on the hardware is 50MHz, so I divided it by 490196 to get 102Hz clock but the clock speed is two times faster when I set the duty cycle to 50% signal…
Gordon Z
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Find Maximum Number present in Verilog array

I have tried writing a small verilog module that will find the maximum of 10 numbers in an array. At the moment I am just trying to verify the correctness of the module without going into specific RTL methods that will to do such a task. I am just…
Arslan Majid
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Synthesis error of Array Multiplication with an input

Hello I am trying a small section of a project code where the equation is multiplying input with all values of array and then adding them up in one final output. module arraywithinput(input in, output reg [11:0] out0 ); reg [7:0]…
Arslan Majid
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How to write directly to FPGA peripherals from SoC?

I'm working on an Altera Cyclone V SoC. I'm attempting to write directly to FPGA peripherals from my SoC, however, the hwlib library only contains the function alt_write_word, which I understand that this function writes to the cache first before…
LowK
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DE-10 FFMPEG Raw YCbCr 4:2:2 Frame to PNG or Video leads to bad result

So i am trying to record analog video from analog-video in port of the DE10-standard board. the raw frames are 4:2:2 720x480 hence frame size should be 720*480 * 2 = 691200bytes,however i get 2 more bytes with hex value 0 at the beginning of the…
Anouar Touati
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How can i reduce number of ALMs in my VHDL design?

I'm trying to implement an alarm module for the digital clock in VHDL. I have written architecture for it, but when I run Compilation I get too many Adaptive Logic Modules (around 2000), which I think is too much. I will post my code below. I think…
Aleksandar Simonović
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