Questions tagged [fsm]

Acronym for Finite State Machine.

Finite state machine, finite state automata, or state machine, is used in computer science or logic theory to represent a finite number of states and the transitions between states.

Finite state machines are commonly used in parsing and matching strings, so it accepts certain types of strings (such as those representing an integer), and a language (set of strings) is regular if and only if it can be represented as a finite state machine.

An example of a finite state machine implementation in pseudocode, accepting all decimal integers:

state = 0;
digits = "152341264"; // Some sequence of decimal digits
for (k = 0; k < len(digits); k++) {
    switch (state) {
    case 0: // Initial state
        if (digits[k] is a decimal digit)
            state = 1;
        else
            state = 2;
        break;
    case 1: // Digit found, also an accepting state
        if (digits[k] is a decimal digit)
            state = 1;
        else
            state = 2;
        break;
    case 2: // Dead state
        break;
    }
}
FSM accepts the string digits if it finishes at state 1.

Finite state machines represent all the regular languages, or Type 3 languages, which are the lowest in the Chomsky hierarchy, below the context-free (Type 2) languages, which is below the context-sensitive (Type 1) languages, which is below the recursively enumerable (Type 0) languages.

Wikipedia page

The tag is also known like on stackoverflow.

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Under one package : compiler fails to read other class

I have three java files in one package : 'Receiver'. CMReceiverMutant.java CMReceiverMutantContext.java TestDriver.java Here is my TestDriver.java package Receiver; public class TestDriver{ public static void main (String[] args){ …
Shieryn
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Mini processor's FSM stuck in branch equal loop

We're writing a mini processor that parses information according to instructions written to its' memory. The first instruction (address 0 in memory) in our testbench is a while loop written as a branch equal: if (delimeter == 0) jump 0. In order to…
efalk
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How do I find the error sequence in Finite State Machine?

I'd like to verify the FSM correctness by verification in the verilog. for example, let we got the below FSM. always @(*) begin win_n_st = win_c_st; case(win_c_st) IDLE : begin if(winapi_start) …
grander3
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Moore machine, Verilog

I want to implement a MOORE FSM that finds the min and max of an array of 10 elements by using 2 always blocks,both of them use the same states but on different halves of the array. Does it work if I use the same state names in both always blocks…
Comp23555
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Dealing with lots of outputs in a finite state machine verilog

So I'm trying to implement my first FSM, and I'm getting very confused. The codes a bit long, so let me summarize: I start with declaring inputs and outputs Then state declarations (I have five plus three placeholders) Then Current state…
qasddd
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Modelsim Altera VHDL MEMORY ROM

I am confused on to why my VHDL design is not working. I am to create a top.vhd file that will program an FPGA board to display addresses 0 through 15 and the corresponding values to each address. When I simulate my design, all the clocks and resets…
Shaunbaum
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Verilog Synchronous state machine

I'm trying to design this state machine in verilog: I was have: `timescale 1ns/1ns module labEightMachine(y, x,clk,clr) output y; input [1:2] x; input clk, clr; reg [1:2] q; reg y; …
drade13
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Simple program crash

I tried to implement a very simple FSM in C++. Problem is, that this program will crash immediately, after executing. I am new to C++ so I can't find any bug here. Can anyone help? Thanks in advance! #include using namespace std; class…
Markus
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Non deterministic finite state machine in java for complex CRM logic

Was looking at implementing Non-deterministic finite state machine in Java. Have checked easyflow and many other such libraries but they offer is Deterministic finite state machine. Eg. Use case. A user is in suspended state and has bill due of 100$…
ManMohan Vyas
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Identifying when to use FSM in verilog

I understand FSM, how they are constructed and implemented in verilog and the different kinds (Mealy vs Moore) but I have a problem in identifying when to actually use a FSM to solve a verilog problem ?? Are there any guidelines ? Thank you
mohanadelnokaly
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Nexys3 interface to a VmodTFT

I'm trying to interface a Nexys3 board with a VmodTFT via a VHDCI connector. I am pretty new to FPGA design, and although I have experience with micro-controllers. I am trying to approach the whole problem as a FSM. However, I've been stuck on this…
Manu
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Verilog Code, Sequential Multiplier using add and shift

this is my verilog code for a sequential add / shift multiplier. I am receiving "XXXXXXX" as an output, if I set reset to high, I receive all zeroes as an output. Can someone please help me identify what I am doing wrong? Thank you for any…
user3533556
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Verilog Arithmetic Equation System Exercise

I am new to Verilog and I found some interesting exercises to work on but there is this one exercise I am stuck on, can anyone help me ??? The exercise: Implement an arithmetic equation system which, when given some values at its inputs, will give…
Techflow
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How do I make a passcode FSM when the inputs are buttons?

I am trying to write a FSM in System Verilog that acts as a password detector. The password will be inputted using 4 buttons labeled b1, b2, b3, b4. The correct passcode is b1-b2-b3-b4. This is my logic and code for the first two states: module…
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How do I use goto with swtich in C? (FSM)

Let's say I have this code switch(x) { region_1: case a: ... case b: goto region_1: region_2: case c: ... case d: goto region_2 default: ... } Is it possible in C to have such a recursion-like…
user15307601
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