Verilog Arithmetic Equation System Exercise

Question

I am new to Verilog and I found some interesting exercises to work on but there is this one exercise I am stuck on, can anyone help me ???

The exercise:

Implement an arithmetic equation system which, when given some values at its inputs, will give the solution for that equation. The pseudo-code of the system is given as follows:

t1 := in1 * in2  
t2 := 3 + in3  
t3 := 3 + in4  
t4 := t1 - t2  
out1 := in2 * t3  
out2 := in1 * t4

There are two types of ALUs that are available for use in this system. The first type can perform addition and subtraction (+/-) operations. You can select the operation you want the ALU to perform using a select signal. The second type of ALUs only performs multiplication operations (*). You have only three adder/subractor ALUs and two multiplier ALUs.

IMPLEMENTATION:

Before implementing the system, you should draw a paper design for the system by following these steps:
1) Identify all the inputs of the system
2) Identify all the registers needed and their inputs
3) Identify all the functional units needed, and their inputs.
4) Determine if any multiplexer are needed at the functional unit inputs
5) Determine all the control signals needed in your design
6) Design the Finite State Machine that is needed to control these signals
7) Determine all the wires needed in your system.

VERILOG IMPLEMENTATION:
In this section you are required to build the 4-bit arithmetic equation system using Verilog by following these steps:
1) Implement all the 4-bit components needed in the design in separate modules (ALUs, MUXs, and REGs).
2) Create an FSM based controller that will guide the datapath through the desired behavior specified in the pseudo code.
3) Simulate the FSM to make sure it is outputting the required pattern of control signals
4) Create a system module, which has a clock button input and a reset button input. This module implements the design of the arithmetic equation solver and contains an instance of the FSM that controls it.
5) Compile your design and debug ALL errors.
6) Simulate the design for different values of Inputs, and make sure your design is working properly.

The Code:

module ALU(in1,in2,select,out);
input [3:0] in1,in2;
input select;
output[3:0] out;
reg [3:0] out;
always @ (in1,in2,select)
    begin
    if(select==0) out=in1+in2;
    else out=in1-in2;
end
endmodule;  


module ALU(in1,in2,out);
input [3:0]  in1,in2;
output [3:0] out;
reg [3:0] out;
always @ (in1,in2)
    begin
    out=in1*in2;
end
endmodule;  


module Register(in,clock,out);
input [3:0] in;
reg [3:0] out;
input clock;
output[3:0] out;
always@(posedge clock)
begin
out=in;
end
endmodule;  


module MUX(in1,in2,select,out);
input select;
output[3:0] out :
input [3:0] in1,in2;
always @(in1,in2,select)
begin
case(select)
0:out=in1;
1:out=in2;
end

endmodule;

And here's where I don't know what to do:

module FSM(clk, reset, select, out1, out2,in1,in2,in3,in4);

input clk,reset,in1,in2,in3,in4;
output select, out1, out2;
reg select, out1,out2;
reg [1:0] state;
reg [1:0] nextstate;

parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;

// State Register

always @(negedge clk or negedge reset)
if (reset == 0) state <= S0;
else state <= nextstate;

// Next State Logic
always @(state)
case (state)

S0: 
     begin
     //?!
                        MUX m1(in3,in4,1,out);
                        ALU a1(3,out,0);
                        nextstate <= S1;
     end
S1:
     begin
     end
S2: 
     begin
                        nextstate <= S3;
     end

S3: 
     begin
                        nextstate <=S0;
     end

default: nextstate <= S0;
endcase

endmodule;

P.S: In my design I have only was able to use 1 ALU that performs multiplication operations and another that performs addition and subtraction operations. Should I provide the design ?

I have implemented both of the ALU modules, the Mux module, and the register module but I don't know how to implement the ALU several times for different inputs ! ( knowing that you can use a max of 2 multiplication ALUs) — Techflow, May 27 '14 at 08:32
@Techflow Could you please show some code to enable others to see what have you actually done and find out where you were stuck on? — e19293001, May 28 '14 at 07:12

score 0 · Answer 1 · answered May 28 '14 at 20:55

You seem confused about the difference between using a module with multiple inputs, and instantiating multiple modules.

First of all, you cannot instantiate a module inside a case statement:

S0: 
     begin
     //?!
                        MUX m1(in3,in4,1,out);  //WRONG
                        ALU a1(3,out,0);        //WRONG
                        nextstate <= S1;
     end
S1:

If you can only have one ALU somewhere, then you instantiate that ALU outside of any procedural blocks. Then in your case statement, you assign the inputs to the module to the inputs you want. It might look something like this:

module FSM;
...
MUX m1(mux_in_a, mux_in_b, mux_sel, mux_out);
ALU a1(alu_in_a, alu_in_b, alu_out); 

// Next State Logic
always @(state)
case (state)
S0: 
     begin
         mux_in_a = in3;
         mux_in_b = in4;
         mux_sel = 1;

         alu_in_a = 3;
         alu_in_b = mux_out;

         nextstate = S1; //don't use nonblocking in combinatorial logic
     end
S1:

So now even though you only have one ALU and one MUX, you pick which inputs get driven to those modules based on the state.

Yes, I kind of figured that out on my own. Thanks alot anyway and sorry for the trouble ! — Techflow, May 29 '14 at 20:49

Verilog Arithmetic Equation System Exercise

The exercise:

1 Answers1