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We're writing a mini processor that parses information according to instructions written to its' memory.

The first instruction (address 0 in memory) in our testbench is a while loop written as a branch equal: if (delimeter == 0) jump 0.

In order to differentiate between the case of waiting for delimeter and a general case of branch equal (or branch not equal), we added a specific waiting_for_delimeter signal but the instruction fetching takes a clock cycle and because the pipeline inserts a NOP (no operation instruction) for a taken branch, in the next clock waiting_for_delimeter cannot be 1 because it "sees" a NOP and not the branch equal instruction.

Can someone please help us to solve this?

Thanks!

Simulation Waves

Lotus91
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efalk
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  • which language are you talking about? Can you provide more code? – Serge Aug 07 '17 at 14:38
  • I'm writing in Verilog – efalk Aug 07 '17 at 16:29
  • [please see relevant code here][1] [1]: https://i.stack.imgur.com/cRDUn.png – efalk Aug 07 '17 at 16:35
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    there is no while loop in this code. there is no 'if'. there is no 'jump' instruction in verilog. Please formulate your question correctly with all supporting code samples, preferably **not** as images. – Serge Aug 07 '17 at 16:59

1 Answers1

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I didn't understand from your question if the signal waiting_for_delimiter sees the branch, gets set to 1, and then reset to zero because of the NOP, or it's never get sets because it never sees the branch.

For the first case:

If you want to "remember" the signal waiting_for_delimiter should be 1 at the next cycle, just sample it using a FF:

reg waiting_for_delimiter_r1;

always @(posedge clk or posedge rst) 
     if (rst)
        waiting_for_delimiter_r1 <= 1'b0;
     else
        waiting_for_delimiter_r1 <= waiting_for_delimiter;

This way, on the next cycle you will have the proper indication in waiting_for_delimiter_r1.

For the second case:

Follow the same approach, and sample the instruction or the indication that the branch was taken. Use this sampling in the waiting_for_delimiter logic.

EEliaz
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